Data Sheet
ADF4157
SPECIFICATIONS
AVDD = DVDD = 2.7 V to 3.3 V; VP = AVDD to 5.5 V; AGND = DGND = 0 V; TA = TMIN to TMAX, unless otherwise noted;
dBm referred to 50 Ω.
Table 1.
Parameter
B Version1
Unit
Test Conditions/Comments
RF CHARACTERISTICS (3 V)
RF Input Frequency (RFIN)
0.5/6.0
GHz min/max
−10 dBm/0 dBm min/max; for lower frequencies, ensure slew rate
(SR) > 400 V/µs
REFERENCE CHARACTERISTICS
REFIN Input Frequency
REFIN Input Sensitivity
10/300
0.4/AVDD
0.7/AVDD
10
MHz min/max
V p-p min/max
V p-p min/max
pF max
For fREFIN < 10 MHz, ensure slew rate > 50 V/µs
For 10 MHz < fREFIN < 250 MHz, biased at AVDD/22
For 250 MHz < fREFIN < 300 MHz, biased at AVDD/22
REFIN Input Capacitance
REFIN Input Current
PHASE DETECTOR
Phase Detector Frequency3
CHARGE PUMP
100
µA max
32
MHz max
ICP Sink/Source
Programmable
High Value
Low Value
Absolute Accuracy
RSET Range
ICP Three-State Leakage Current
Matching
ICP vs. VCP
ICP vs. Temperature
LOGIC INPUTS
5
mA typ
µA typ
% typ
kΩ min/max
nA typ
% typ
With RSET = 5.1 kΩ
312.5
2.5
2.7/10
1
2
2
2
With RSET = 5.1 kΩ
Sink and source current
0.5 V < VCP < VP – 0.5
0.5 V < VCP < VP – 0.5
VCP = VP/2
% typ
% typ
VINH, Input High Voltage
VINL, Input Low Voltage
IINH/IINL, Input Current
CIN, Input Capacitance
LOGIC OUTPUTS
VOH, Output High Voltage
VOH, Output High Voltage
VOL, Output Low Voltage
POWER SUPPLIES
AVDD
1.4
0.6
1
V min
V max
µA max
pF max
10
1.4
VDD – 0.4
0.4
V min
V min
V max
Open-drain 1 kΩ pull-up to 1.8 V
CMOS output chosen
IOL = 500 µA
2.7/3.3
AVDD
AVDD/5.5
29
V min/max
DVDD
VP
IDD
V min/V max
mA max
23 mA typical
Low Power Sleep Mode
NOISE CHARACTERISTICS
10
µA typ
Normalized Phase Noise Floor
−211
dBc/Hz typ
PLL loop B/W = 500 kHz;
measured at 100 kHz
10 kHz offset; normalized to 1 GHz
@ 10 MHz PFD frequency
@ 25 MHz PFD frequency
@ VCO output
4
(PNSYNTH
)
Normalized 1/f Noise (PN1_f)5
Phase Noise Floor6
−110
−137
−133
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
Phase Noise Performance7
5800 MHz Output8
−87
dBc/Hz typ
@ 2 kHz offset, 25 MHz PFD frequency
1 Operating temperature of B version is −40°C to +85°C.
2 AC-coupling ensures AVDD/2 bias.
3 Guaranteed by design. Sample tested to ensure compliance.
4 The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log(N) (where N is the N divider
value) and 10 log(FPFD). PNSYNTH = PNTOT − 10 log(FPFD) − 20 log(N).
5 The PLL phase noise is composed of 1/f (flicker) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency, FRF,
and at a frequency offset f is given by PN = PN1_f + 10 log(10 kHz/f) + 20 log(FRF/1 GHz). Both the normalized phase noise floor and flicker noise are modeled in ADIsimPLL.
6 The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20logN (where N is the N divider value).
7 The phase noise is measured with the EV-ADF4157SD1Z and the Agilent E5052A phase noise system.
8 fREFIN = 100 MHz; fPFD = 25 MHz; offset frequency = 2 kHz; RFOUT = 5800.25 MHz; N = 232; loop bandwidth = 20 kHz.
Rev. D | Page 3 of 24