ADF4106BCP

更新时间： 2024-02-26 07:37:30

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
20页	227K
描述
PLL Frequency Synthesizer

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数据手册

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ADF4106BCP 数据手册

ADF4106

3.5

= 3V

3.0

2.5

2.0

1.5

1.0

0.5

= 5V

= 5mA

–2

–4

–6

100

150

200

250

300

0.5

1.0

1.5

2.0

2.5

– V

3.0

3.5

4.0

4.5

5.0

PRESCALER OUTPUT FREQUENCY

TPC 13. DI_DDvs. Prescaler Output Frequency

TPC 14. Charge Pump Output Characteristics

CIRCUIT DESCRIPTION

PRESCALER (P/P + 1)

REFERENCE INPUT SECTION

The dual modulus prescaler (P/P + 1), along with the A and

B counters, enables the large division ratio, N, to be realized

(N = BP + A). The dual-modulus prescaler, operating at CML

levels, takes the clock from the RF input stage and divides it

down to a manageable frequency for the CMOS A and B

counters. The prescaler is programmable. It can be set in soft-

ware to 8/9, 16/17, 32/33 or 64/65. It is based on a synchronous

4/5 core. There is a minimum divide ratio possible for fully

contiguous output frequencies. This minimum is determined by

P, the prescaler value and is given by: (P²– P).

The Reference Input stage is shown in Figure 2. SW1 and SW2

are normally-closed switches. SW3 is normally-open. When

Powerdown is initiated, SW3 is closed and SW1 and SW2 are

opened. This ensures that there is no loading of the REF_INpin

on power-down.

POWER-DOWN

CONTROL

100kꢁ

A AND B COUNTERS

SW2

The A and B CMOS counters combine with the dual modulus

prescaler to allow a wide ranging division ratio in the PLL feed-

back counter. The counters are specified to work when the

prescaler output is 300 MHz or less. Thus, with an RF input

frequency of 4.0 GHz, a prescaler value of 16/17 is valid but a

value of 8/9 is not valid.

TO R COUNTER

REF

SW1

BUFFER

SW3

NC = NO CONNECT

Pulse Swallow Function

Figure 2. Reference Input Stage

The A and B counters, in conjunction with the dual modulus

prescaler make it possible to generate output frequencies which

are spaced only by the Reference Frequency divided by R. The

equation for the VCO frequency is as follows:

RF INPUT STAGE

The RF input stage is shown in Figure 3. It is followed by a 2-stage

limiting amplifier to generate the CML clock levels needed for the

prescaler.

f_REFIN

f_VCO= [(P × B)+ A]×

BIAS

1.6V

f_VCO

Output Frequency of external voltage controlled

oscillator (VCO).

Preset modulus of dual modulus prescaler

(8/9, 16/17, etc.,).

GENERATOR

500ꢁ

Preset Divide Ratio of binary 13-bit counter

(3 to 8191).

Preset Divide Ratio of binary 6-bit swallow

counter (0 to 63).

External reference frequency oscillator.

f_REFIN

AGND

Figure 3. RF Input Stage

–8–

REV. 0

1...5 6 789 10 11...20

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