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ADF4002BRUZ-RL PDF预览

ADF4002BRUZ-RL

更新时间: 2024-02-22 16:51:29
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
24页 457K
描述
Phase Detector/Frequency Synthesizer

ADF4002BRUZ-RL 技术参数

是否无铅: 含铅是否Rohs认证: 符合
生命周期:Active包装说明:TSSOP, TSSOP16,.25
针数:16Reach Compliance Code:compliant
风险等级:5.65模拟集成电路 - 其他类型:PLL FREQUENCY SYNTHESIZER
JESD-30 代码:R-PDSO-G16长度:5 mm
功能数量:1端子数量:16
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP16,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH座面最大高度:1.2 mm
最大供电电流 (Isup):6 mA最大供电电压 (Vsup):3.3 V
最小供电电压 (Vsup):2.7 V标称供电电压 (Vsup):3 V
表面贴装:YES技术:BICMOS
温度等级:INDUSTRIAL端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
宽度:4.4 mmBase Number Matches:1

ADF4002BRUZ-RL 数据手册

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ADF4002  
TABLE OF CONTENTS  
Features .............................................................................................. 1  
MUXOUT and Lock Detect.........................................................9  
Input Shift Register .......................................................................9  
Latch Maps and Descriptions ....................................................... 10  
Latch Summary........................................................................... 10  
Reference Counter Latch Map.................................................. 11  
N Counter Latch Map................................................................ 12  
Function Latch Map................................................................... 13  
Initialization Latch Map ............................................................ 14  
The Function Latch.................................................................... 15  
The Initialization Latch ............................................................. 16  
Applications..................................................................................... 17  
Very Low Jitter Encode Clock for High Speed Converters... 17  
PFD............................................................................................... 18  
Interfacing ................................................................................... 18  
PCB Design Guidelines for Chip Scale Package .................... 18  
Outline Dimensions....................................................................... 20  
Ordering Guide .......................................................................... 21  
Applications....................................................................................... 1  
General Description......................................................................... 1  
Functional Block Diagram .............................................................. 1  
Revision History ............................................................................... 2  
Specifications..................................................................................... 3  
Timing Characteristics ................................................................ 4  
Absolute Maximum Ratings............................................................ 5  
Thermal Characteristics .............................................................. 5  
ESD Caution.................................................................................. 5  
Pin Configurations and Function Descriptions ........................... 6  
Typical Performance Characteristics ............................................. 7  
Theory of Operation ........................................................................ 8  
Reference Input Section............................................................... 8  
RF Input Stage............................................................................... 8  
N Counter...................................................................................... 8  
R Counter ...................................................................................... 8  
Phase Frequency Detector (PFD) and Charge Pump.............. 8  
REVISION HISTORY  
4/06—Revision 0: Initial Version  
Rev. 0 | Page 2 of 24  
 

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