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ADCMP561BRQ

更新时间： 2024-11-22 22:39:03
品牌 Logo 应用领域
亚德诺 - ADI 比较器
页数 文件大小 规格书
16页 465K
描述
Dual High Speed PECL Comparators

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ADCMP561BRQ 数据手册

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Dual High Speed PECL Comparators  
ADCMP561/ADCMP562  
FEATURES  
FUNCTIONAL BLOCK DIAGRAM  
HYS*  
Differential PECL compatible outputs  
700 ps propagation delay input to output  
75 ps propagation delay dispersion  
Input common-mode range: –2.0 V to +3.0 V  
Robust input protection  
NONINVERTING  
Q OUTPUT  
INPUT  
ADCMP561/  
ADCMP562  
INVERTING  
Q OUTPUT  
INPUT  
Differential latch control  
Internal latch pull-up resistors  
Power supply rejection greater than 85 dB  
700 ps minimum pulse width  
LATCH ENABLE  
LATCH ENABLE  
INPUT  
INPUT  
*ADCMP562 ONLY  
Figure 1.  
1.5 GHz equivalent input rise time bandwidth  
Typical output rise/fall time of 500 ps  
ESD protection > 4kV HBM, >200V MM  
Programmable hysteresis  
V
V
DD  
1
2
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
DD  
QA  
QA  
QB  
1
2
3
4
5
6
7
8
16  
QB  
QA  
QA  
QB  
3
APPLICATIONS  
15 QB  
ADCMP562  
TOP VIEW  
(Not to Scale)  
V
GND  
LEB  
LEB  
4
DD  
Automatic test equipment  
High speed instrumentation  
Scope and logic analyzer front ends  
Window comparators  
High speed line receivers  
Threshold detection  
14 GND  
13 LEB  
12 LEB  
V
LEA  
5
DD  
ADCMP561  
TOP VIEW  
(Not to Scale)  
LEA  
LEA  
6
LEA  
V
V
7
EE  
CC  
11  
V
V
–INA  
+INA  
–INB  
+INB  
HYSB  
CC  
10 –INB  
+INB  
8
EE  
–INA  
+INA  
9
9
HYSA  
10  
Peak detection  
High speed triggers  
Figure 2. ADCMP561 16-Lead QSOP  
Figure 3. ADCMP562 20-Lead QSOP  
Patient diagnostics  
Disk drive read channel detection  
Hand-held test instruments  
Zero-crossing detectors  
Line receivers and signal restoration  
Clock drivers  
GENERAL DESCRIPTION  
The ADCMP561/ADCMP562 are high speed comparators  
fabricated on Analog Devices’ proprietary XFCB process. The  
devices feature a 700 ps propagation delay with less than 75 ps  
overdrive dispersion. Dispersion, a measure of the difference in  
propagation delay under differing overdrive conditions, is a  
particularly important characteristic of comparators. A separate  
programmable hysteresis pin is available on the ADCMP562.  
are fully compatible with PECL 10 K and 10 KH logic families.  
The outputs provide sufficient drive current to directly drive  
transmission lines terminated in 50 Ω to VDD − 2 V. A latch  
input, which is included, permits tracking, track-and-hold, or  
sample-and-hold modes of operation. The latch input pins  
contain internal pull-ups that set the latch in tracking mode  
when left open.  
A differential input stage permits consistent propagation delay  
with a wide variety of signals in the common-mode range from  
−2.0 V to +3.0 V. Outputs are complementary digital signals that  
The ADCMP561/ADCMP562 are specified over the industrial  
temperature range (−40°C to +85°C).  
Rev. A  
Information furnished by Analog Devices is believed to be accurate and reliable.  
However, no responsibility is assumed by Analog Devices for its use, nor for any  
infringements of patents or other rights of third parties that may result from its use.  
Specifications subject to change without notice. No license is granted by implication  
or otherwise under any patent or patent rights of Analog Devices. Trademarks and  
registered trademarks are the property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
Fax: 781.326.8703  
www.analog.com  
© 2004 Analog Devices, Inc. All rights reserved.  
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