Datasheet > ADCLK954BCPZ-REEL7

ADCLK954BCPZ-REEL7

更新时间： 2024-02-24 06:09:47

品牌	Logo	应用领域
亚德诺 - ADI		半导体逻辑集成电路驱动时钟
页数	文件大小	规格书
12页	294K
描述
Two Selectable Inputs, 12 LVPECL Outputs, SiGe Clock Fanout Buffer

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ADCLK954BCPZ-REEL7 数据手册

ADCLK954

INPUT TERMINATION OPTIONS

REF

50Ω

CLK

CONNECT V TO V

REF

Figure 19. Interfacing to CML Inputs

Figure 21. AC Coupling Differential Signals Inputs, Such As LVDS

REF

50Ω

REF

CLK

50Ω

– 2V

CLK

CONNECT V , V

, AND CLK. PLACE A BYPASS

CAPACITOR FROM V TO GROUND.

REF

ALTERNATIVELY, V , V

, AND CLK CAN BE

REF

CONNECTED, GIVING A CLEANER LAYOUT AND

A 180º PHASE SHIFT.

CONNECT V TO V − 2V.

Figure 20. Interfacing to PECL Inputs

Figure 22. Interfacing to AC-Coupled Single-Ended Inputs

Rev. A | Page 11 of 12

1...8 9 101112

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型号	品牌	替代类型	描述	数据表
ADCLK954BCPZ	ADI	完全替代	Two Selectable Inputs, 12 LVPECL Outputs, SiGe Clock Fanout Buffer

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