Datasheet > ADCLK954BCPZ-REEL7

ADCLK954BCPZ-REEL7

更新时间： 2024-01-01 13:20:01

品牌	Logo	应用领域
亚德诺 - ADI		半导体逻辑集成电路驱动时钟
页数	文件大小	规格书
12页	294K
描述
Two Selectable Inputs, 12 LVPECL Outputs, SiGe Clock Fanout Buffer

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ADCLK954

input signal due to parasitic inductance in the termination

return path. If the inputs are dc-coupled to a source, take care to

ensure that the pins are within the rated input differential and

common-mode ranges.

CLOCK INPUT SELECT (IN_SEL) SETTINGS

A Logic 0 on the IN_SEL pin selects the Input CLK0 and

Input

CLK0

and Input

. A Logic 1 on the IN_SEL pin selects Input CLK1

CLK1

If the return is floated, the device exhibits a 100 ꢁ cross termi-

nation, but the source must then control the common-mode

voltage and supply the input bias currents.

PCB LAYOUT CONSIDERATIONS

The ADCLK954 buffer is designed for very high speed applica-

tions. Consequently, high speed design techniques must be used

to achieve the specified performance. It is critically important

to use low impedance supply planes for both the negative supply

(V_EE) and the positive supply (V_CC) planes as part of a multilayer

board. Providing the lowest inductance return path for switching

currents ensures the best possible performance in the target

application.

There are ESD/clamp diodes between the input pins to prevent

the application from developing excessive offsets to the input

transistors. ESD diodes are not optimized for best ac perfor-

mance. When a clamp is required, it is recommended that

appropriate external diodes be used.

Exposed Metal Paddle

The exposed metal paddle on the ADCLK954 package is both

an electrical connection and a thermal enhancement. For the

device to function properly, the paddle must be properly

attached to the V_EEpower plane.

The following references to GND plane assume that the V_EE

power plane is grounded for LVPECL operation. Note that for

ECL operation, the V_CCpower plane becomes the ground plane.

It is also important to adequately bypass the input and output

supplies. Place a 1 μF electrolytic bypass capacitor within several

inches of each V_CCpower supply pin to the GND plane. In

addition, place multiple high quality 0.001 μF bypass capacitors

as close as possible to each of the V_CCsupply pins and connect

the capacitors to the GND plane with redundant vias. Carefully

select high frequency bypass capacitors for minimum induc-

tance and ESR. To improve the effectiveness of the bypass at

high frequencies, minimize parasitic layout inductance. Also,

avoid discontinuities along input and output transmission lines

that can affect jitter performance.

When properly mounted, the ADCLK954 also dissipates heat

through its exposed paddle. The PCB acts as a heat sink for the

ADCLK954. The PCB attachment must provide a good thermal

path to a larger heat dissipation area. This requires a grid of vias

from the top layer down to the V_EEpower plane (see Figure 18).

The ADCLK954 evaluation board (ADCLK954/PCBZ) provides

an example of how to attach the part to the PCB.

In a 50 Ω environment, input and output matching have a

VIAS TO V POWER

significant impact on performance. The buffer provides internal

PLANE

CLKx

50 Ω termination resistors for both CLKx and

inputs.

Normally, the return side is connected to the reference pin that is

provided. Carefully bypass the termination potential using

ceramic capacitors to prevent undesired aberrations on the

Figure 18. PCB Land for Attaching Exposed Paddle

Rev. A | Page 10 of 12

1...7 8 91011 12

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ADCLK954BCPZ-REEL7 替代型号

型号	品牌	替代类型	描述	数据表
ADCLK954BCPZ	ADI	完全替代	Two Selectable Inputs, 12 LVPECL Outputs, SiGe Clock Fanout Buffer

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