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ADC12DL066CIVS/NOPB PDF预览

ADC12DL066CIVS/NOPB

更新时间: 2024-02-22 06:01:42
品牌 Logo 应用领域
美国国家半导体 - NSC 转换器
页数 文件大小 规格书
24页 503K
描述
IC DUAL 1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP64, TQFP-64, Analog to Digital Converter

ADC12DL066CIVS/NOPB 技术参数

是否Rohs认证: 符合生命周期:Transferred
包装说明:TFQFP, TQFP64,.47SQReach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:8.11最大模拟输入电压:1.5 V
最小模拟输入电压:0.5 V最长转换时间:0.4 µs
转换器类型:ADC, PROPRIETARY METHODJESD-30 代码:S-PQFP-G64
JESD-609代码:e3长度:10 mm
最大线性误差 (EL):0.0732%湿度敏感等级:3
模拟输入通道数量:1位数:12
功能数量:2端子数量:64
最高工作温度:85 °C最低工作温度:-40 °C
输出位码:BINARY, OFFSET BINARY, 2'S COMPLEMENT BINARY输出格式:PARALLEL, WORD
封装主体材料:PLASTIC/EPOXY封装代码:TFQFP
封装等效代码:TQFP64,.47SQ封装形状:SQUARE
封装形式:FLATPACK, THIN PROFILE, FINE PITCH峰值回流温度(摄氏度):260
电源:3.3 V认证状态:Not Qualified
采样速率:66 MHz采样并保持/跟踪并保持:SAMPLE
座面最大高度:1.2 mm子类别:Analog to Digital Converters
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn)端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:40宽度:10 mm
Base Number Matches:1

ADC12DL066CIVS/NOPB 数据手册

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February 1, 2008  
ADC12DL066  
Dual 12-Bit, 66 Msps, 450 MHz Input Bandwidth A/D  
Converter w/Internal Reference  
General Description  
Features  
The ADC12DL066 is a dual, low power monolithic CMOS  
analog-to-digital converter capable of converting analog input  
signals into 12-bit digital words at 66 Megasamples per sec-  
ond (Msps), minimum. This converter uses a differential,  
pipeline architecture with digital error correction and an on-  
chip sample-and-hold circuit to minimize die size and power  
consumption while providing excellent dynamic performance  
and a 450 MHz Full Power Bandwidth. Operating on a single  
3.3V power supply, the ADC12DL066 achieves 10.7 effective  
bits and consumes just 686 mW at 66 Msps, including the  
reference current. The Power Down feature reduces power  
consumption to 75 mW.  
Choice of Binary or 2’s complement output format  
Single +3.3V Supply Operation  
Outputs 2.4V to 3.3V Compatible  
Pin Compatible with ADC12D040  
Power Down Mode  
Internal/External Reference  
Key Specifications  
Resolution  
DNL  
SNR (fIN = 10 MHz)  
SFDR (fIN = 10 MHz)  
Data Latency  
12 Bits  
±0.5 LSB (typ)  
66 dB (typ)  
81 dB (typ)  
6 Clock Cycles  
The differential inputs provide a full scale differential input  
swing equal to 2 times VREF with the possibility of a single-  
ended input. Full use of the differential input is recommended  
for optimum performance. The digital outputs from the two  
ADCs are available on separate 12-bit buses with an output  
data format choice of offset binary or two’s complement.  
Power Consumption  
Operating  
Power Down Mode  
686 mW (typ)  
75 mW (typ)  
To ease interfacing to lower voltage systems, the digital out-  
put driver power pins of the ADC12DL066 can be connected  
to a separate supply voltage in the range of 2.4V to the digital  
supply voltage.  
Applications  
Ultrasound and Imaging  
Instrumentation  
This device is available in the 64-lead TQFP package and will  
operate over the industrial temperature range of −40°C to  
+85°C. An evaluation board is available to ease the evalua-  
tion process.  
Communications Receivers  
Sonar/Radar  
xDSL  
Cable Modems  
DSP Front Ends  
Connection Diagram  
20055201  
TRI-STATE® is a registered trademark of National Semiconductor Corporation.  
© 2008 National Semiconductor Corporation  
200552  
www.national.com  

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