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ADC12DL065CIVS/NOPB PDF预览

ADC12DL065CIVS/NOPB

更新时间： 2023-09-03 20:31:04
品牌 Logo 应用领域
德州仪器 - TI 转换器模数转换器
页数 文件大小 规格书
35页 974K
描述
双通道、12 位、65MSPS 模数转换器 (ADC) | PAG | 64 | -40 to 85

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ADC12DL065CIVS/NOPB 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Active零件包装代码：QFP
包装说明：GREEN, PLASTIC, TQFP-64针数：64
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：1 week
风险等级：1.26Is Samacsys：N
最大模拟输入电压：2 V最小模拟输入电压：-2 V
最长转换时间：0.46 µs转换器类型：ADC, PROPRIETARY METHOD
JESD-30 代码：S-PQFP-G64JESD-609代码：e3
长度：10 mm最大线性误差 (EL)：0.0415%
湿度敏感等级：3模拟输入通道数量：2
位数：12功能数量：1
端子数量：64最高工作温度：85 °C
最低工作温度：-40 °C输出位码：OFFSET BINARY, 2'S COMPLEMENT BINARY
输出格式：PARALLEL, WORD封装主体材料：PLASTIC/EPOXY
封装代码：TFQFP封装等效代码：TQFP64,.47SQ
封装形状：SQUARE封装形式：FLATPACK, THIN PROFILE, FINE PITCH
峰值回流温度（摄氏度）：260电源：3.3 V
认证状态：Not Qualified采样速率：65 MHz
采样并保持/跟踪并保持：SAMPLE座面最大高度：1.2 mm
子类别：Analog to Digital Converters最大压摆率：108 mA
标称供电电压：3.3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Matte Tin (Sn)端子形式：GULL WING
端子节距：0.5 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：10 mm
Base Number Matches：1

ADC12DL065CIVS/NOPB 数据手册

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ADC12DL065  
www.ti.com  
SNAS249D –MARCH 2005–REVISED APRIL 2013  
ADC12DL065 Dual 12-Bit, 65 MSPS, 3.3V, 360mW A/D Converter  
Check for Samples: ADC12DL065  
1
FEATURES  
DESCRIPTION  
The ADC12DL065 is a dual, low power monolithic  
CMOS analog-to-digital converter capable of  
converting analog input signals into 12-bit digital  
words at 65 Megasamples per second (MSPS). This  
converter uses a differential, pipeline architecture with  
digital error correction and an on-chip sample-and-  
hold circuit to minimize power consumption while  
providing excellent dynamic performance and a 250  
MHz Full Power Bandwidth. Operating on a single  
+3.3V power supply, the ADC12DL065 achieves 11.0  
effective bits at nyquist and consumes just 360 mW  
at 65 MSPS, including the reference current. The  
Power Down feature reduces power consumption to  
36 mW.  
2
•
•
•
•
•
•
•
Single +3.3V Supply operation  
Internal Sample-and-Hold  
Internal Reference  
Outputs 2.4V to 3.6V Compatible  
Power Down Mode  
Duty Cycle Stabilizer  
Multiplexed Output Mode  
APPLICATIONS  
•
•
•
•
•
•
•
Ultrasound and Imaging  
Instrumentation  
Communications Receivers  
Sonar/Radar  
The differential inputs provide a full scale differential  
input swing equal to 2 times VREF with the possibility  
of a single-ended input. Full use of the differential  
input is recommended for optimum performance. The  
digital outputs from the two ADC's are available on a  
single multiplexed 12-bit bus or on separate buses.  
Duty cycle stabilization and output data format are  
selectable using a quad state function pin. The output  
data can be set for offset binary or two's complement.  
xDSL  
Cable Modems  
DSP Front Ends  
KEY SPECIFICATIONS  
•
•
•
•
•
•
Resolution: 12 Bits  
To ease interfacing to lower voltage systems, the  
digital output driver power pins of the ADC12DL065  
can be connected to a separate supply voltage in the  
range of 2.4V to the analog supply voltage. This  
device is available in the 64-lead TQFP package and  
will operate over the industrial temperature range of  
−40°C to +85°C. An evaluation board is available to  
ease the evaluation process.  
DNL: ±0.4 LSB (typ)  
SNR (fIN = 10 MHz): 69 dB (typ)  
SFDR (fIN = 10 MHz): 86 dB (typ)  
Data Latency: 7 Clock Cycles  
Power Consumption  
–
–
Operating: 360 mW (typ)  
Power Down Mode: 36 mW (typ)  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
2
All trademarks are the property of their respective owners.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2005–2013, Texas Instruments Incorporated  
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 		selecting amplifiers, adcs, and clocks for high-performance signal paths

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