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ADC12DL040_13

更新时间: 2024-01-13 02:45:28
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德州仪器 - TI /
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描述
ADC12DL040 Dual 12-Bit, 40 MSPS, 3V, 210mW A/D Converter

ADC12DL040_13 数据手册

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ADC12DL040  
www.ti.com  
SNAS250D FEBRUARY 2005REVISED APRIL 2013  
ADC12DL040 Dual 12-Bit, 40 MSPS, 3V, 210mW A/D Converter  
Check for Samples: ADC12DL040  
1
FEATURES  
DESCRIPTION  
The ADC12DL040 is a dual, low power monolithic  
CMOS analog-to-digital converter capable of  
converting analog input signals into 12-bit digital  
words at 40 Megasamples per second (MSPS). This  
converter uses a differential, pipeline architecture with  
digital error correction and an on-chip sample-and-  
hold circuit to minimize power consumption while  
providing excellent dynamic performance and a 250  
MHz Full Power Bandwidth. Operating on a single  
+3.0V power supply, the ADC12DL040 achieves 11.1  
effective bits at nyquist and consumes just 210 mW  
at 40 MSPS, including the reference current. The  
Power Down feature reduces power consumption to  
36 mW.  
23  
Single +3.0V Supply Operation  
Internal Sample-and-Hold  
Internal Reference  
Outputs 2.4V to 3.6V Compatible  
Power Down Mode  
Duty Cycle Stabilizer  
Multiplexed Output Mode  
APPLICATIONS  
Ultrasound and Imaging  
Instrumentation  
Communications Receivers  
Sonar/Radar  
The differential inputs provide a full scale differential  
input swing equal to 2 times VREF with the possibility  
of a single-ended input. Full use of the differential  
input is recommended for optimum performance. The  
digital outputs from the two ADC's are available on a  
single multiplexed 12-bit bus or on separate buses.  
Duty cycle stabilization and output data format are  
selectable using a quad state function pin. The output  
data can be set for offset binary or two's complement.  
xDSL  
Cable Modems  
DSP Front Ends  
KEY SPECIFICATIONS  
Resolution 12 Bits  
To ease interfacing to lower voltage systems, the  
digital output driver power pins of the ADC12DL040  
can be connected to a separate supply voltage in the  
range of 2.4V to the analog supply voltage.  
DNL ±0.3 LSB (typ)  
SNR (fIN = 10 MHz) 69 dB (typ)  
SFDR (fIN = 10 MHz) 85 dB (typ)  
Data Latency 7 Clock Cycles  
Power Consumption  
This device is available in the 64-lead TQFP package  
and will operate over the industrial temperature range  
of 40°C to +85°C. An evaluation board is available  
to ease the evaluation process.  
Operating 210 mW (typ)  
Power Down Mode 36 mW (typ)  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
2
3
TRI-STATE is a registered trademark of National Semiconductor Corporation.  
All other trademarks are the property of their respective owners.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2005–2013, Texas Instruments Incorporated  

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