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ADC1251CIJ

更新时间： 2024-11-19 22:09:35
品牌 Logo 应用领域
美国国家半导体 - NSC 转换器
页数 文件大小 规格书
16页 302K
描述
Self-Calibrating 12-Bit Plus Sign A/D Converter with Sample-and-Hold

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中文翻译

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ADC1251CIJ 数据手册

 浏览型号ADC1251CIJ的Datasheet PDF文件第2页浏览型号ADC1251CIJ的Datasheet PDF文件第3页浏览型号ADC1251CIJ的Datasheet PDF文件第4页浏览型号ADC1251CIJ的Datasheet PDF文件第5页浏览型号ADC1251CIJ的Datasheet PDF文件第6页浏览型号ADC1251CIJ的Datasheet PDF文件第7页 
December 1994  
ADC1251 Self-Calibrating 12-Bit Plus Sign  
A/D Converter with Sample-and-Hold  
Y
8-bit mP/DSP interface  
General Description  
Y
a
Bipolar input range with a single 5V reference  
No missing codes over temperature  
The ADC1251 is a CMOS 12-bit plus sign successive ap-  
proximation analog-to-digital converter. On request, the  
ADC1251 goes through a self-calibration cycle that adjusts  
for any zero, full scale, or linearity errors. The ADC1251 also  
has the ability to go through an Auto-Zero cycle that cor-  
rects the zero error during every conversion.  
Y
Y
TTL/MOS input/output compatible  
Key Specifications  
Y
Resolution  
12 bits plus sign  
8 ms (max)  
Y
Conversion Time  
The analog input to the ADC1251 is tracked and held by the  
internal circuitry, so an external sample-and-hold is not re-  
quired. The ADC1251 has an S/H control input which direct-  
ly controls the track-and-hold state of the A/D. A unipolar  
Y
Sampling Rate  
83 kHz (max)  
Y
g
g
0.6 LSB ( 0.0146%) (max)  
Linearity Error  
Zero Error  
Y
Y
Y
g
1 LSB (max)  
a
analog input voltage range (0 to 5V) or a bipolar range  
g
Full Scale Error  
Power Consumption  
1.5 LSB (max)  
b
a
g
5V to 5V) can be accommodated with 5V supplies.  
(
@
g
5V  
113 mW (max)  
The 13-bit data result is available on the eight outputs of the  
ADC1251 in two bytes, high-byte first and sign extended.  
The digital inputs and outputs are compatible with TTL or  
CMOS logic levels.  
Applications  
Y
Digital signal processing  
Y
Y
High resolution process control  
Instrumentation  
Features  
Y
Self-calibration provides excellent temperature stability  
Y
Internal sample-and-hold  
Simplified Block Diagram  
Connection Diagram  
Dual-In-Line Package  
TL/H/11024–2  
Top View  
Ordering Information  
Industrial  
Package  
s
s
a
b
(
40 C  
§
T
A
85 C)  
§
ADC1251BIJ,  
J24A  
ADC1251CIJ  
TL/H/11024–1  
Military  
Package  
s
s
a
b
(
55 C  
§
T
A
125 C)  
§
ADC1251CMJ,  
ADC1251CMJ/883  
J24A  
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.  
C
1995 National Semiconductor Corporation  
TL/H/11024  
RRD-B30M115/Printed in U. S. A.  
1234567...16

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