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ADC1251CIJ PDF预览

ADC1251CIJ

更新时间： 2024-01-24 19:55:57
品牌 Logo 应用领域
美国国家半导体 - NSC 转换器
页数 文件大小 规格书
16页 302K
描述
Self-Calibrating 12-Bit Plus Sign A/D Converter with Sample-and-Hold

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中文翻译

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ADC1251CIJ 技术参数

生命周期：Obsolete包装说明：DIP,
Reach Compliance Code：unknownECCN代码：3A001.A.2.C
HTS代码：8542.39.00.01风险等级：5.82
最大模拟输入电压：5.55 V最小模拟输入电压：-4.55 V
最长转换时间：15.65 µs转换器类型：ADC, SUCCESSIVE APPROXIMATION
JESD-30 代码：R-GDIP-T24最大线性误差 (EL)：0.0244%
标称负供电电压：-5 V模拟输入通道数量：1
位数：12功能数量：1
端子数量：24最高工作温度：125 °C
最低工作温度：-55 °C输出位码：BINARY
输出格式：PARALLEL, WORD封装主体材料：CERAMIC, GLASS-SEALED
封装代码：DIP封装形状：RECTANGULAR
封装形式：IN-LINE认证状态：Not Qualified
采样并保持/跟踪并保持：SAMPLE筛选级别：MIL-STD-883
座面最大高度：4.572 mm标称供电电压：5 V
表面贴装：NO技术：CMOS
温度等级：MILITARY端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
宽度：15.24 mmBase Number Matches：1

ADC1251CIJ 数据手册

 浏览型号ADC1251CIJ的Datasheet PDF文件第1页浏览型号ADC1251CIJ的Datasheet PDF文件第2页浏览型号ADC1251CIJ的Datasheet PDF文件第3页浏览型号ADC1251CIJ的Datasheet PDF文件第5页浏览型号ADC1251CIJ的Datasheet PDF文件第6页浏览型号ADC1251CIJ的Datasheet PDF文件第7页 
AC Electrical Characteristics  
The following specifications apply for DV  
CC  
b
e
e a  
; all other limits T  
e b  
e
§
e
t
f
AV  
CC  
5.0V, V  
5.0V, t  
20 ns unless otherwise specified.  
e
T 25 C. (Notes 6 and 7)  
J
r
e
e
e
Boldface limits apply for T  
T
T
MIN  
to T  
A
J
MAX  
A
Typical  
(Note 9)  
Limit  
Units  
Symbol  
Parameter  
Clock Frequency  
Conditions  
(Notes 10, 19)  
(Limit)  
f
MHz  
CLK  
0.5  
6.0  
MHz(min)  
MHz(max)  
3.5  
Clock Duty Cycle  
50  
%
40  
60  
%(min)  
%(max)  
a
)
CLK  
t
t
Conversion Time Using WR  
to Start a Conversion  
27(1/f  
)
)
27(1/f  
250 ns  
250 ns  
(max)  
ms(max)  
ms(max)  
(max)  
C
CLK  
e
e
‘‘1’’  
f
f
3.5 MHz, AZ  
7.7  
7.95  
CLK  
e
e
‘‘0’’  
1.75 MHz, AZ  
15.4  
15.65  
CLK  
e
a
)
CLK  
Conversion Time Using S/H  
to Start a Conversion  
AZ  
‘‘1’’  
34(1/f  
CLK  
34(1/f  
C
e
e
‘‘1’’  
f
3.5 MHz, AZ  
9.7  
3.5  
9.95  
3.5  
ms(max)  
ms(min)  
CLK  
e
50X  
t
t
Acquisition Time (Note 15)  
Internal Acquisition Time  
R
A
SOURCE  
IA  
7(1/f  
)
7(1/f  
)
(max)  
CLK  
CLK  
(When Using WR Control Only)  
a
a
250 ns  
t
t
t
Auto Zero Time  
Acquisition Time  
33(1/f  
)
33(1/f  
)
(max)  
ms(max)  
ns(max)  
ns(max)  
(max)  
ZA  
CLK  
CLK  
e
f
1.75 MHz  
18.8  
19.05  
350  
CLK  
Delay from Hold Command  
to Falling Edge of EOC  
Using WR Control  
Using S/H Control  
200  
100  
D(EOC)L  
CAL  
150  
Calibration Time  
1399(1/f  
399  
)
1399 (1/f )  
CLK  
CLK  
e
f
3.5 MHz  
400  
ms(max)  
ns(min)  
ns(min)  
CLK  
t
t
t
Calibration Pulse Width  
(Note 16)  
60  
200  
W(CAL)L  
W(WR)L  
ACC  
Minimum WR Pulse Width  
60  
200  
e
e
Maximum Access Time  
(Delay from Falling Edge of  
RD to Output Data Valid)  
C
100 pF  
L
50  
30  
95  
70  
ns(max)  
ns(max)  
e
100 pF  
t , t  
0H 1H  
TRI-STATE Control  
(Delay from Rising Edge of  
RD to Hi-Z State)  
R
1 kX, C  
L
L
t
t
Maximum Delay from Falling Edge  
of RD or WR to Reset of INT  
PD(INT)  
100  
30  
175  
60  
ns(max)  
ns(min)  
Delay between Successive RD Pulses  
RR  
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is  
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed  
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test  
conditions.  
Note 2: All voltages are measured with respect to AGND and DGND, unless otherwise specified.  
b
k
l
(AV or DV ), the current at that pin should be limited to  
CC CC  
Note 3: When the input voltage (V ) at any pin exceeds the power supply rails (V  
IN  
V
or V  
IN  
IN  
5 mA. The 20 mA maximum package input current rating allows the voltage at any four pins, with an input current limit of 5 mA, to simultaneously exceed the power  
supply voltages.  
a
Note 4: The power dissipation of this device under normal operation should never exceed 191 mW (Quiescent Power Dissipation  
output). Caution should be taken not to exceed absolute maximum power rating when the device is operating in severe fault condition (ex. when any inputs or  
outputs exceed the power supply). The maximum power dissipation must be derated at elevated temperatures and is dictated by T (maximum junction  
1 TTL Load on each digital  
Jmax  
temperature), i (package junction to ambient thermal resistance), and T (ambient temperature). The maximum allowable power dissipation at any temperature  
JA  
A
e
b
e
150 C, and the typical thermal  
Jmax  
is P  
Dmax  
(T  
T
)/i or the number given in the Absolute Maximum Ratings, whichever is lower. For this device, T  
§
Jmax  
A
JA  
resistance (i ) of the ADC1251 with CMJ, BIJ, and CIJ suffixes when board mounted is 51 C/W.  
§
JA  
Note 5: Human body model, 100 pF discharged through a 1.5 kX resistor.  
4
1234567...16

中文翻译

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