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ADC10DL065CIVS PDF预览

ADC10DL065CIVS

更新时间: 2024-11-25 03:25:35
品牌 Logo 应用领域
美国国家半导体 - NSC 转换器模数转换器
页数 文件大小 规格书
26页 1088K
描述
Dual 10-Bit, 65 MSPS, 3.3V, 370mW A/D Converter

ADC10DL065CIVS 技术参数

是否Rohs认证: 不符合生命周期:Transferred
包装说明:TQFP-48Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.45Is Samacsys:N
最大模拟输入电压:3.6 V最小模拟输入电压:3 V
最长转换时间:0.107 µs转换器类型:ADC SUBSYSTEM
JESD-30 代码:S-PQFP-G48JESD-609代码:e0
长度:10 mm最大线性误差 (EL):0.0977%
湿度敏感等级:3模拟输入通道数量:2
位数:10功能数量:2
端子数量:48最高工作温度:85 °C
最低工作温度:-40 °C输出位码:BINARY, OFFSET BINARY, 2'S COMPLEMENT BINARY
输出格式:PARALLEL, WORD封装主体材料:PLASTIC/EPOXY
封装代码:TFQFP封装等效代码:TQFP64,.47SQ
封装形状:SQUARE封装形式:FLATPACK, THIN PROFILE, FINE PITCH
峰值回流温度(摄氏度):260电源:3.3 V
认证状态:Not Qualified采样速率:65 MHz
采样并保持/跟踪并保持:SAMPLE座面最大高度:1.2 mm
子类别:Analog to Digital Converters标称供电电压:3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:40
宽度:10 mmBase Number Matches:1

ADC10DL065CIVS 数据手册

 浏览型号ADC10DL065CIVS的Datasheet PDF文件第2页浏览型号ADC10DL065CIVS的Datasheet PDF文件第3页浏览型号ADC10DL065CIVS的Datasheet PDF文件第4页浏览型号ADC10DL065CIVS的Datasheet PDF文件第5页浏览型号ADC10DL065CIVS的Datasheet PDF文件第6页浏览型号ADC10DL065CIVS的Datasheet PDF文件第7页 
June 2006  
ADC10DL065  
Dual 10-Bit, 65 MSPS, 3.3V, 370mW A/D Converter  
General Description  
Features  
n Single +3.3V supply operation  
n Internal sample-and-hold  
n Internal reference  
The ADC10DL065 is a dual, low power monolithic CMOS  
analog-to-digital converter capable of converting analog in-  
put signals into 10-bit digital words at 65 Megasamples per  
second (MSPS). This converter uses a differential, pipeline  
architecture with digital error correction and an on-chip  
sample-and-hold circuit to minimize power consumption  
while providing excellent dynamic performance and a 250  
MHz Full Power Bandwidth. Operating on a single +3.3V  
power supply, the ADC10DL065 achieves 9.8 effective bits  
at nyquist and consumes just 370 mW at 65 MSPS, including  
the reference current. The Power Down feature reduces  
power consumption to 36 mW.  
n Outputs 2.4V to 3.6V compatible  
n Power down mode  
n Duty Cycle Stabilizer  
n Multiplexed Output Mode  
Key Specifications  
n Resolution  
n DNL  
10 Bits  
0.16 LSB (typ)  
61 dB (typ)  
85 dB (typ)  
7 Clock Cycles  
The differential inputs provide a full scale differential input  
swing equal to 2 times VREF with the possibility of a single-  
ended input. Full use of the differential input is recom-  
mended for optimum performance. The digital outputs from  
the two ADC’s are available on a single multiplexed 10-bit  
bus or on separate buses. Duty cycle stabilization and output  
data format are selectable using a quad state function pin.  
The output data can be set for offset binary or two’s comple-  
ment.  
n SNR (fIN = 10 MHz)  
n SFDR (fIN = 10 MHz)  
n Data Latency  
n Power Consumption  
n -- Operating  
370 mW (typ)  
36 mW (typ)  
n -- Power Down Mode  
Applications  
n Ultrasound and Imaging  
n Instrumentation  
n Communications Receivers  
n Sonar/Radar  
To ease interfacing to lower voltage systems, the digital  
output driver power pins of the ADC10DL065 can be con-  
nected to a separate supply voltage in the range of 2.4V to  
the analog supply voltage. This device is available in the  
64-lead TQFP package and will operate over the industrial  
temperature range of −40˚C to +85˚C. An evaluation board is  
available to ease the evaluation process.  
n xDSL  
n DSP Front Ends  
Connection Diagram  
20148601  
TRI-STATE® is a registered trademark of National Semiconductor Corporation.  
© 2006 National Semiconductor Corporation  
DS201486  
www.national.com  

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