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AD9957_07

更新时间： 2022-04-23 23:00:11
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
60页 1183K
描述
1 GSPS Quadrature Digital Upconverter with 18-Bit IQ Data Path and 14-Bit DAC

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AD9957_07 数据手册

 浏览型号AD9957_07的Datasheet PDF文件第52页浏览型号AD9957_07的Datasheet PDF文件第53页浏览型号AD9957_07的Datasheet PDF文件第54页浏览型号AD9957_07的Datasheet PDF文件第56页浏览型号AD9957_07的Datasheet PDF文件第57页浏览型号AD9957_07的Datasheet PDF文件第58页 
AD9957  
QDUC profiles control: DDS frequency (32 bits), DDS phase  
PROFILE REGISTERS  
offset (16 bits), output amplitude scaling (8 bits), CCI filter  
interpolation factor, inverse CCI bypass, and spectral invert.  
The QDUC profiles also selectively apply to the interpolating  
DAC operating mode: only output scaling, CCI filter  
interpolation factor, and inverse CCI bypass apply; all others  
(DDS frequency, output amplitude scaling, and spectral invert)  
are ignored.  
There are eight consecutive serial I/O addresses (0x0E to 0x15)  
dedicated to device profiles. All eight profile registers are either  
single tone profiles or QDUC profiles depending on the device  
operating mode specified by CFR1 Bits<25:24>. During  
operation, the active profile register is determined via the  
external PROFILE<2:0> pins.  
Single tone profiles control: DDS frequency (32 bits), DDS  
phase offset (16 bits), and DDS amplitude scaling (14 bits).  
Profile<0:7> Register—Single Tone  
Address 0x0E to 0x15, eight bytes are assigned to this register.  
Table 27. Bit Descriptions for Profile<0:7> Registers—Single Tone  
Bits  
Mnemonic  
Description  
63:62  
61:48  
47:32  
31:0  
Not Available  
Amplitude Scale Factor  
Phase Offset Word  
Frequency Tuning Word  
This 14-bit number controls the DDS output amplitude.  
This 16-bit number controls the DDS phase offset.  
This 32-bit number controls the DDS frequency.  
Profile<0:7> Register—QDUC  
Address 0x0E to 0x15, eight bytes are assigned to this register.  
Table 28. Bit Descriptions for Profile<0:7> Registers—QDUC  
Bits  
63:58  
57  
Mnemonic  
Description  
CC Interpolation Rate  
Spectral Invert  
This 6-bit number is the rate interpolation factor for the CCI filter.  
0: The modulator output takes the form: I(t) × cos( ct) – Q(t) × sin( ct).  
1: The modulator output takes the form: I(t) × cos( ct) + Q(t) × sin( ct).  
0: The inverse CCI filter is enabled.  
56  
Inverse CCI Bypass  
1: The inverse CCI filter is bypassed.  
55:48  
47:32  
31:0  
Output Scale Factor  
Phase Offset Word  
Frequency Tuning Word  
This 8-bit number controls the output amplitude.  
This 16-bit number controls the DDS phase offset.  
This 32-bit number controls the DDS frequency.  
RAM Register  
Address 0x16, four bytes are assigned to this register.  
Table 29. Bit Descriptions for RAM Register  
Bits  
Mnemonic  
Description  
31:0  
RAM Word  
The number of 32-bit words written to RAM is defined by the start and end address in  
RAM Segment Register 0 or RAM Segment Register 1.  
GPIO Config Register  
Address 0x18, one byte is assigned to this register.  
Table 30. Bit Descriptions for GPIO Config Register  
Bits  
Mnemonic  
Description  
15:0  
Configuration Bits  
See the General-Purpose I/O (GPIO) Port section for details; default is 0x0000.  
Rev. 0 | Page 55 of 60  
 
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