Datasheet > AD9857_17

AD9857_17

更新时间： 2022-02-26 12:47:31

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
41页	893K
描述
CMOS 200 MSPS 14-Bit Quadrature Digital Upconverter

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AD9857_17 数据手册

AD9857

Parameter

Temp

Test Level

Min

Typ

Max

Unit

POWER SUPPLY V_SCURRENT³(all power specifications at

V_DD= 3.3 V, 25°C, REFCLK = 200 MHz)

Full Operating Conditions

160 MHz Clock (×16)

120 MHz Clock (×12)

Burst Operation (25%)

Single-Tone Mode

25°C

540

445

345

395

265

615

515

400

450

310

Power-Down Mode

Full-Sleep Mode

13.5

¹Wake-up time refers to recovery from full-sleep mode. The longest time required is for the reference clock multiplier PLL to lock up (if it is being used). The wake-up

time assumes that there is no capacitor on DAC_BP, and that the recommended PLL loop filter values are used. The state of the reference clock multiplier lock can be

determined by observing the signal on the PLL_LOCK pin.

²SYSCLK refers to the actual clock frequency used on-chip by the AD9857. If the reference clock multiplier is used to multiply the external reference frequency, the

SYSCLK frequency is the external frequency multiplied by the reference clock multiplier multiplication factor. If the reference clock multiplier is not used, the SYSCLK

frequency is the same as the external REFCLK frequency.

³CIC = 2, INV SINC ON, FTW = 40%, PLL OFF, auto power-down between burst On, TxENABLE duty cycle = 25%.

Rev. C| Page 7 of 40

1...5 6 789 10 11...41

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