12-Output Clock Generator with
Integrated 2.5 GHz VCO
Data Sheet
AD9517-1
FEATURES
FUNCTIONAL BLOCK DIAGRAM
CP
LF
Low phase noise, phase-locked loop (PLL)
On-chip VCO tunes from 2.30 GHz to 2.65 GHz
External VCO/VCXO to 2.4 GHz optional
1 differential or 2 single-ended reference inputs
Reference monitoring capability
Automatic revertive and manual reference
switchover/holdover modes
Accepts LVPECL, LVDS, or CMOS references to 250 MHz
Programmable delays in path to PFD
Digital or analog lock detect, selectable
2 pairs of 1.6 GHz LVPECL outputs
Each output pair shares a 1-to-32 divider with coarse
phase delay
Additive output jitter: 225 fs rms
Channel-to-channel skew paired outputs of <10 ps
2 pairs of 800 MHz LVDS clock outputs
Each output pair shares two cascaded 1-to-32 dividers
with coarse phase delay
REF1
REF2
STATUS
MONITOR
REFIN
CLK
VCO
DIVIDER
AND MUXs
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
DIV/Φ
DIV/Φ
DIV/Φ
DIV/Φ
LVPECL
LVPECL
Δt
Δt
Δt
Δt
DIV/Φ
DIV/Φ
LVDS/CMOS
LVDS/CMOS
SERIAL CONTROL PORT
AND
AD9517-1
DIGITAL LOGIC
Additive output jitter: 275 fs rms
Figure 1.
Fine delay adjust (Δt) on each LVDS output
Each LVDS output can be reconfigured as two 250 MHz
CMOS outputs
Automatic synchronization of all outputs on power-up
Manual output synchronization available
Available in a 48-lead LFCSP
The AD9517-1 features four LVPECL outputs (in two pairs)
and four LVDS outputs (in two pairs). Each LVDS output can
be reconfigured as two CMOS outputs. The LVPECL outputs
operate to 1.6 GHz, the LVDS outputs operate to 800 MHz, and
the CMOS outputs operate to 250 MHz.
For applications that require additional outputs, a crystal reference
input, zero-delay, or EEPROM for automatic configuration at
startup, the AD9520 and AD9522 are available. In addition,
the AD9516 and AD9518 are similar to the AD9517 but have
a different combination of outputs.
APPLICATIONS
Low jitter, low phase noise clock distribution
10/40/100 Gb/sec networking line cards, including SONET,
Synchronous Ethernet, OTU2/3/4
Forward error correction (G.710)
Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs
High performance wireless transceivers
Each pair of outputs has dividers that allow both the divide
ratio and coarse delay (or phase) to be set. The range of division
for the LVPECL outputs is 1 to 32. The LVDS/CMOS outputs
allow a range of divisions up to a maximum of 1024.
ATE and high performance instrumentation
GENERAL DESCRIPTION
The AD9517-1 is available in a 48-lead LFCSP and can be
operated from a single 3.3 V supply. An external VCO, which
requires an extended voltage range, can be accommodated
by connecting the charge pump supply (VCP) to 5 V. A separate
LVPECL power supply can be from 2.5 V to 3.3 V (nominal).
The AD9517-11 provides a multi-output clock distribution
function with subpicosecond jitter performance, along with an
on-chip PLL and VCO. The on-chip VCO tunes from 2.30 GHz
to 2.65 GHz. Optionally, an external VCO/VCXO of up to
2.4 GHz can be used.
The AD9517-1 is specified for operation over the industrial
range of −40°C to +85°C.
The AD9517-1 emphasizes low jitter and phase noise to
maximize data converter performance, and it can benefit other
applications with demanding phase noise and jitter requirements.
1 AD9517 is used throughout the data sheet to refer to all the members of
the AD9517 family. However, when AD9517-1 is used, it refers to that
specific member of the AD9517 family.
Rev. E
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license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
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Tel: 781.329.4700 ©2007–2013 Analog Devices, Inc. All rights reserved.
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