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AD9518-0BCPZ-REEL7 PDF预览

AD9518-0BCPZ-REEL7

更新时间: 2024-11-05 20:39:03
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亚德诺 - ADI 驱动逻辑集成电路
页数 文件大小 规格书
64页 767K
描述
6-Output Clock Generator with Integrated 2.8 GHz VCO

AD9518-0BCPZ-REEL7 数据手册

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6-Output Clock Generator with  
Integrated 2.8 GHz VCO  
AD9518-0  
FUNCTIONAL BLOCK DIAGRAM  
FEATURES  
CP  
LF  
Low phase noise, phase-locked loop (PLL)  
On-chip VCO tunes from 2.55 GHz to 2.95 GHz  
External VCO/VCXO to 2.4 GHz optional  
1 differential or 2 single-ended reference inputs  
Reference monitoring capability  
Auto and manual reference switchover/holdover modes  
Autorecover from holdover  
Accepts LVPECL, LVDS, or CMOS references to 250 MHz  
Programmable delays in path to PFD  
Digital or analog lock detect, selectable  
3 pairs of 1.6 GHz LVPECL outputs  
REF1  
REF2  
STATUS  
MONITOR  
REFIN  
CLK  
VCO  
DIVIDER  
AND MUXs  
OUT0  
OUT1  
OUT2  
OUT3  
OUT4  
OUT5  
DIV/Φ  
DIV/Φ  
DIV/Φ  
LVPECL  
LVPECL  
LVPECL  
Each output pair shares a 1-to-32 divider with coarse  
phase delay  
Additive output jitter 225 fs rms  
SERIAL CONTROL PORT  
AND  
Channel-to-channel skew paired outputs of <10 ps  
Automatic synchronization of all outputs on power-up  
Manual synchronization of outputs as needed  
Serial control port  
AD9518-0  
DIGITAL LOGIC  
Figure 1.  
Available in 48-lead LFCSP  
APPLICATIONS  
Low jitter, low phase noise clock distribution  
Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs  
High performance wireless transceivers  
10/40/100 Gb/sec networking line cards, including SONET,  
Synchronous Ethernet, OTU2/3/4  
The AD9518-0 features six LVPECL outputs (in three pairs).  
The LVPECL outputs operate to 1.6 GHz.  
Each pair of outputs has dividers that allow both the divide ratio  
and coarse delay (or phase) to be set. The range of division for  
the LVPECL outputs is 1 to 32.  
High performance instrumentation  
Broadband infrastructure  
ATE  
The AD9518-0 is available in a 48-lead LFCSP and can be  
operated from a single 3.3 V supply. An external VCO, which  
requires an extended voltage range, can be accommodated  
by connecting the charge pump supply (VCP) to 5 V. A separate  
LVPECL power supply can be from 2.5 V to 3.3 V (nominal).  
GENERAL DESCRIPTION  
The AD9518-01 provides a multi-output clock distribution  
function with subpicosecond jitter performance, along with an  
on-chip PLL and VCO. The on-chip VCO tunes from 2.55 GHz  
to 2.95 GHz. Optionally, an external VCO/VCXO of up to  
2.4 GHz can be used.  
The AD9518-0 is specified for operation over the industrial  
range of −40°C to +85°C.  
1 AD9518 is used throughout to refer to all the members of the AD9518  
family. However, when AD9518-0 is used, it is referring to that specific  
member of the AD9518 family.  
The AD9518-0 emphasizes low jitter and phase noise to  
maximize data converter performance, and it can benefit other  
applications with demanding phase noise and jitter requirements.  
Rev. A  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
rights of third parties that may result from its use. Specifications subject to change without notice. No  
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.  
Trademarks and registeredtrademarks arethe property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
www.analog.com  
Fax: 781.461.3113 ©2007–2010 Analog Devices, Inc. All rights reserved.  
 

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