Datasheet > AD9520

AD9520

更新时间： 2022-04-19 23:05:31

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
3页	390K
描述
Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers

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AD9520 数据手册

Circuit Note

CN-0121

Devices Connected/Referenced

Circuit Designs Using Analog Devices Products

Apply these product pairings quickly and with confidence.

For more information and/or support call 1-800-AnalogD

(1-800-262-5643) or visit www.analog.com/circuit.

AD9910

1 GSPS Direct Digital Synthesizer (DDS)

Clock Generator and Distribution IC

High Speed LVDS Clock Fanout Buffer

AD9520

ADCLK846

Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers

The circuit in Figure 1 demonstrates how to synchronize four

AD9910 1 GSPS, DDS chips using the AD9520 clock generator

and the ADCLK846 clock fanout buffer. The result is precise

phase alignment between the clock and output signals of four

AD9910 devices.

CIRCUIT FUNCTION AND BENEFITS

Synchronization of multiple DDS devices allows precise digital

tuning control of the phase and amplitude across multiple

frequency carriers. This type of control is useful in radar

applications and quadrature (I/Q) upconversion for side-band

suppression.

ADCLK846

LVDS

LEVELS

LVDS

LEVELS

CLK1

+ SYNC_IN

– SYNC_IN

SYNC_CLK

AOUT

AD9910

(MASTER)

AD9520

PECL

LEVELS

REF CLK

IO_UPDATE

+ SYNC_OUT

– SYNC_OUT

REF CLK

SYNC_CLK

AOUT

AD9910

(SLAVE)

IO_UPDATE

CMOS

LEVEL

CH1

CH2

CH3

CH4

+ SYNC_IN

CMOS

LEVELS

DG2020A

– SYNC_IN

DATA

GENERATOR

REF CLK

SYNC_CLK

AOUT

IO_UPDATE

CLOCK

AD9910

(SLAVE)

+ SYNC_IN

– SYNC_IN

REF CLK

SYNC_CLK

AOUT

IO_UPDATE

AD9910

(SLAVE)

+ SYNC_IN

– SYNC_IN

Figure 1. Setup for Synchronization of Multiple AD9910’s (Simplified Schematic: Decoupling, Power, and All Connections Not Shown)

Rev. A

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