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AD9277BSVZ

更新时间: 2024-10-28 06:36:15
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亚德诺 - ADI /
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48页 1028K
描述
Octal LNA/VGA/AAF/14-Bit ADC and CW I/Q Demodulator

AD9277BSVZ 数据手册

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Octal LNA/VGA/AAF/14-Bit ADC  
and CW I/Q Demodulator  
AD9277  
FEATURES  
APPLICATIONS  
8 channels of LNA, VGA, AAF, ADC, and I/Q demodulator  
Low noise preamplifier (LNA)  
Medical imaging/ultrasound  
Automotive radar  
Input-referred noise: 0.75 nV/√Hz typical at 5 MHz  
(gain = 21.3 dB)  
PRODUCT HIGHLIGHTS  
SPI-programmable gain: 15.6 dB/17.9 dB/21.3 dB  
Single-ended input: VIN maximum = 733 mV p-p/  
550 mV p-p/367 mV p-p  
Dual-mode active input impedance matching  
Bandwidth (BW) > 100 MHz  
Full-scale (FS) output: 4.4 V p-p differential  
Variable gain amplifier (VGA)  
Attenuator range: −42 dB to 0 dB  
Postamp gain: 21 dB/24 dB/27 dB/30 dB  
Linear-in-dB gain control  
Antialiasing filter (AAF)  
Programmable second-order LPF from 8 MHz to 18 MHz  
Programmable HPF  
Analog-to-digital converter (ADC)  
14 bits at 10 MSPS to 50 MSPS  
SNR: 73 dB  
SFDR: 75 dB  
Serial LVDS (ANSI-644, IEEE 1596.3 reduced range link)  
Data and frame clock outputs  
CW mode I/Q demodulator  
1. Small Footprint.  
Eight channels are contained in a small, space-saving  
package. Full TGC path, ADC, and I/Q demodulator  
contained within a 100-lead, 16 mm × 16 mm TQFP.  
2. Low Power.  
In TGC mode, low power of 207 mW per channel  
at 50 MSPS. In CW mode, ultralow power of 94 mW  
per channel.  
3. Integrated High Dynamic Range I/Q Demodulator with  
Phase Rotation.  
4. Ease of Use.  
A data clock output (DCO± ± operates up to 480 MHz  
and supports double data rate (DDR± operation.  
5. User Flexibility.  
Serial port interface (SPI± control offers a wide range of  
flexible features to meet specific system requirements.  
6. Integrated Second-Order Antialiasing Filter.  
This filter is placed before the ADC and is programmable  
from 8 MHz to 18 MHz.  
Individual programmable phase rotation  
Output dynamic range per channel >160 dBFS/√Hz  
Low power: 207 mW per channel at 14 bits/50 MSPS (TGC),  
94 mW per channel for CW Doppler  
Flexible power-down modes  
Overload recovery in <10 ns  
Fast recovery from low power standby mode: <2 μs  
100-lead TQFP_EP  
FUNCTIONAL BLOCK DIAGRAM  
AVDD1 AVDD2  
PDWN STBY  
DRVDD  
LO-A TO LO-H  
I/Q  
8 CHANNELS  
DEMODULATOR  
LOSW-A TO LOSW-H  
LI-A TO LI-H  
DOUTA+ TO DOUTH+  
DOUTA– TO DOUTH–  
14-BIT  
ADC  
SERIAL  
LVDS  
LNA  
VGA  
AAF  
LG-A TO LG-H  
FCO+  
FCO–  
DCO+  
DCO–  
DATA  
RATE  
MULTIPLIER  
SERIAL  
PORT  
INTERFACE  
LO  
REFERENCE  
GENERATION  
Figure 1.  
Rev. 0  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
rights of third parties that may result from its use. Specifications subject to change without notice. No  
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.  
Trademarks and registeredtrademarks arethe property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
Fax: 781.461.3113  
www.analog.com  
©2009 Analog Devices, Inc. All rights reserved.  
 

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