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AD9250

更新时间: 2024-10-29 12:23:51
品牌 Logo 应用领域
亚德诺 - ADI 转换器
页数 文件大小 规格书
44页 1181K
描述
14-Bit, 170 MSPS/250 MSPS, JESD204B,Dual Analog-to-Digital Converter

AD9250 数据手册

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14-Bit, 170 MSPS/250 MSPS, JESD204B,  
Dual Analog-to-Digital Converter  
Data Sheet  
AD9250  
FEATURES  
FUNCTIONAL BLOCK DIAGRAM  
AVDD DRVDD DVDD  
AGND DGND DRGND  
JESD204B Subclass 0 or Subclass 1 coded serial digital outputs  
Signal-to-noise ratio (SNR) = 70.6 dBFS at 185 MHz AIN and  
250 MSPS  
Spurious-free dynamic range (SFDR) = 88 dBc at 185 MHz  
AIN and 250 MSPS  
AD9250  
VIN+A  
VIN–A  
PIPELINE  
JESD-204B  
INTERFACE  
SERDOUT0±  
SERDOUT1±  
14-BIT ADC  
CML, TX  
OUTPUTS  
VCM  
HIGH  
SPEED  
SERIALIZERS  
Total power consumption: 711 mW at 250 MSPS  
1.8 V supply voltages  
VIN+B  
PIPELINE  
14-BIT ADC  
VIN–B  
Integer 1-to-8 input clock divider  
Sample rates of up to 250 MSPS  
CMOS  
DIGITAL  
INPUT/  
CONTROL  
REGISTERS  
PDWN  
OUTPUT  
IF sampling frequencies of up to 400 MHz  
Internal analog-to-digital converter (ADC) voltage reference  
Flexible analog input range  
1.4 V p-p to 2.0 V p-p (1.75 V p-p nominal)  
ADC clock duty cycle stabilizer (DCS)  
95 dB channel isolation/crosstalk  
SYSREF±  
SYNCINB±  
CLK±  
CLOCK  
CMOS  
GENERATION  
FDA  
FDB  
DIGITAL  
INPUT/  
FAST  
DETECT  
RFCLK  
CMOS  
DIGITAL  
OUTPUT  
INPUT/OUTPUT  
SDIO SCLK CS  
RST  
Figure 1.  
Serial port control  
Energy saving power-down modes  
User-configurable, built-in self-test (BIST) capability  
PRODUCT HIGHLIGHTS  
APPLICATIONS  
1. Integrated dual, 14-bit, 170 MSPS/250 MSPS ADC.  
2. The configurable JESD204B output block supports up to  
5 Gbps per lane.  
3. An on-chip, phase-locked loop (PLL) allows users to provide a  
single ADC sampling clock; the PLL multiplies the ADC  
sampling clock to produce the corresponding JESD204B  
data rate clock.  
4. Support for an optional RF clock input to ease system board  
design.  
Diversity radio systems  
Multimode digital receivers (3G)  
TD-SCDMA, WiMAX, WCDMA, CDMA2000, GSM, EDGE, LTE  
DOCSIS 3.0 CMTS upstream receive paths  
HFC digital reverse path receivers  
I/Q demodulation systems  
Smart antenna systems  
Electronic test and measurement equipment  
Radar receivers  
5. Proprietary differential input maintains excellent SNR  
performance for input frequencies of up to 400 MHz.  
6. Operation from a single 1.8 V power supply.  
7. Standard serial port interface (SPI) that supports various  
product features and functions such as controlling the clock  
DCS, power-down, test modes, voltage reference mode, over  
range fast detection, and serial output configuration.  
COMSEC radio architectures  
IED detection/jamming systems  
General-purpose software radios  
Broadband data applications  
Rev. 0  
Document Feedback  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
rightsof third parties that may result fromits use. Specifications subject to change without notice. No  
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.  
Trademarks andregisteredtrademarks are the property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
Technical Support  
©2012 Analog Devices, Inc. All rights reserved.  
www.analog.com  
 
 
 
 

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