Datasheet > AD9234BCPZRL7-1000

AD9234BCPZRL7-1000

更新时间： 2024-10-28 20:56:47

品牌	Logo	应用领域
亚德诺 - ADI		转换器
页数	文件大小	规格书
72页	1611K
描述
12-Bit, 1 GSPS/500 MSPS JESD204B, Dual Analog-to-Digital Converter

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12-Bit, 1 GSPS/500 MSPS JESD204B,

Dual Analog-to-Digital Converter

Data Sheet

AD9234

FEATURES

FUNCTIONAL BLOCK DIAGRAM

AVDD1 AVDD2 AVDD3 AVDD1_SR DVDD DRVDD

SPIVDD

JESD204B (Subclass 1) coded serial digital outputs

1.5 W total power per channel at 1 GSPS (default settings)

SFDR

79 dBFS at 340 MHz (1 GSPS)

85 dBFS at 340 MHz (500 MSPS)

SNR

63.4 dBFS at 340 MHz (A_IN= −1.0 dBFS, 1 GSPS)

65.6 dBFS at 340 MHz (A_IN= −1.0 dBFS, 500 MSPS)

ENOB = 10.4 bits at 10 MHz (1 GSPS)

DNL = 0.16 LSB; INL = 0.35 LSB (1 GSPS)

Noise density

(1.25V) (2.5V) (3.3V)

(1.25V)

(1.25V) (1.25V) (1.8V TO 3.3V)

BUFFER

VIN+A

VIN–A

ADC

CORE

DECIMATE

BY 2

FD_A

SERDOUT0±

SERDOUT1±

SERDOUT2±

SERDOUT3±

SIGNAL

MONITOR

DECIMATE

BY 2

FD_B

VIN+B

VIN–B

ADC

CORE

BUFFER

FAST

DETECT

V_1P0

SYNCINB±

SYSREF±

JESD204B

SUBCLASS 1

CONTROL

CLOCK

GENERATION

AND ADJUST

−151 dBFS/Hz (1 GSPS)

CLK+

CLK–

−150 dBFS/Hz (500 MSPS)

1.25 V, 2.5 V, and 3.3 V dc supply operation

Low swing full-scale input

÷2

÷4

÷8

SIGNAL

SPI CONTROL

MONITOR

PDWN/

STBY

AD9234

1.34 V p-p typical (1 GSPS)

1.63 V p-p typical (500 MSPS)

No missing codes

AGND DRGND DGND SDIO SCLK CSB

Figure 1.

Internal ADC voltage reference

Flexible termination impedance

400 Ω, 200 Ω, 100 Ω, and 50 Ω differential

2 GHz usable analog input full power bandwidth

95 dB channel isolation/crosstalk

Amplitude detect bits for efficient AGC implementation

Differential clock input

Optional decimate by 2 DDC per channel

Differential clock input

Integer clock divide by 1, 2, 4, or 8

Flexible JESD204B lane configurations

Small signal dither

PRODUCT HIGHLIGHTS

1. Low power consumption analog core, 12-bit, 1.0 GSPS dual

analog-to-digital converter (ADC) with 1.5 W per channel.

2. Wide full power bandwidth supports IF sampling of signals

up to 2 GHz.

3. Buffered inputs with programmable input termination

eases filter design and implementation.

4. Flexible serial port interface (SPI) controls various product

features and functions to meet specific system requirements.

5. Programmable fast overrange detection.

6. 9 mm × 9 mm 64-lead LFCSP.

7. Pin compatible with the AD9680 14-bit, 1 GSPS/500 MSPS

APPLICATIONS

dual ADC.

Communications

Diversity multiband, multimode digital receivers

3G/4G, TD-SCDMA, W-CDMA, GSM, LTE

Point to point radio systems

Digital predistortion observation path

General-purpose software radios

Ultrawideband satellite receiver

Instrumentation (spectrum analyzers, network analyzers,

integrated RF test solutions)

Digital oscilloscopes

High speed data acquisition systems

DOCSIS 3.0 CMTS upstream receive paths

HFC digital reverse path receivers

Rev. B

Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rightsof third parties that may result fromits use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks andregisteredtrademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Technical Support

www.analog.com

12 3 4 5 6 7...72

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与AD9234BCPZRL7-1000相关器件

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