12-Bit, 20/40/65 MSPS
3 V A/D Converter
AD9235
Data Sheet
FEATURES
FUNCTIONAL BLOCK DIAGRAM
AVDD
DRVDD
Single 3 V supply operation (2.7 V to 3.6 V)
SNR = 70 dBc to Nyquist at 65 MSPS
SFDR = 85 dBc to Nyquist at 65 MSPS
Low power: 300 mW at 65 MSPS
Differential input with 500 MHz bandwidth
On-chip reference and SHA
VIN+
VIN–
8-STAGE
1 1/2-BIT
PIPELINE
SHA
A/D
MDAC1
4
16
3
REFT
REFB
A/D
DNL = 0.4 LSB
CORRECTION LOGIC
12
Flexible analog input: 1 V p-p to 2 V p-p range
Offset binary or twos complement data format
Clock duty cycle stabilizer
OUTPUT BUFFERS
OTR
D11
AD9235
VREF
D0
CLOCK
DUTY CYCLE
STABILIZER
APPLICATIONS
Ultrasound equipment
IF sampling in communications receivers
IS-95, CDMA-One, IMT-2000
Battery-powered instruments
Hand-held scopemeters
MODE
SELECT
SENSE
REF
SELECT
0.5V
AGND
CLK
PDWN
MODE
DGND
Figure 1.
Low cost digital oscilloscopes
GENERAL DESCRIPTION
can be used with the most significant bit to determine low or
high overflow.
The AD9235 is a family of monolithic, single 3 V supply, 12-bit,
20/40/65 MSPS analog-to-digital converters (ADCs). This
family features a high performance sample-and-hold amplifier
(SHA) and voltage reference. The AD9235 uses a multistage
differential pipelined architecture with output error correction
logic to provide 12-bit accuracy at 20/40/65 MSPS data rates
and guarantee no missing codes over the full operating
temperature range.
Fabricated on an advanced CMOS process, the AD9235 is avail-
able in a 28-lead TSSOP and a 32-lead LFCSP and is specified
over the industrial temperature range (–40°C to +85°C).
PRODUCT HIGHLIGHTS
1. The AD9235 operates from a single 3 V power supply and
features a separate digital output driver supply to accommo-
date 2.5 V and 3.3 V logic families.
2. Operating at 65 MSPS, the AD9235 consumes a low 300 m W.
3. The patented SHA input maintains excellent performance for
input frequencies up to 100 MHz and can be configured for
single-ended or differential operation.
4. The AD9235 pinout is similar to the AD9214-65, a 10-bit,
65 MSPS ADC. This allows a simplified upgrade path from
10 bits to 12 bits for 65 MSPS systems.
The wide bandwidth, truly differential SHA allows a variety of
user-selectable input ranges and offsets including single-ended
applications. It is suitable for multiplexed systems that switch
full-scale voltage levels in successive channels and for sampling
single-channel inputs at frequencies well beyond the Nyquist rate.
Combined with power and cost savings over previously available
ADCs, the AD9235 is suitable for applications in communica-
tions, imaging, and medical ultrasound.
5. The clock DCS maintains overall ADC performance over a
wide range of clock pulse widths.
6. The OTR output bit indicates when the signal is beyond the
selected input range.
A single-ended clock input is used to control all internal
conversion cycles. A duty cycle stabilizer (DCS) compensates
for wide variations in the clock duty cycle while maintaining
excellent overall ADC performance. The digital output data is
presented in straight binary or twos complement formats. An
out-of-range (OTR) signal indicates an overflow condition that
Rev. D
Information furnishedby Analog Devices is believedto be accurate andreliable. However, nore-
sponsibility is assumed by Analog Devices for its use, nor for anyinfringements of patentsor other
rightsofthird partiesthat may result from its use. Specifications subject to change without notice. No
license isgrantedbyimplication or otherwise under anypatent or patent rights of Analog Devices.
Trademarks andregisteredtrademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2012 Analog Devices, Inc. All rights reserved.
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