Quad 12-Bit, 50/65 MSPS
Serial LVDS 3V A/D Converter
AD9229
Preliminary Technical Data
FEATURES
FUNCTIONAL BLOCK DIAGRAM
· Four ADCs in one package
· Serial LVDS digital output data rates (ANSI-644)
· Data clock output provided
· On Chip Reference and SHA
· SNR = 70 dB at Fin up to Nyquist
· Excellent Linearity:
PDWN
AVDD
DRVDD
DRGND
AD9229
12
VIN+A
VIN-A
D1+A
D1-A
Serial
LVDS
Pipeline
ADC
SHA
SHA
SHA
SHA
12
VIN+B
VIN-B
-
-
DNL = ±0.3 LSB (Typical)
INL = ±0.6 LSB (Typical)
Serial
LVDS
D1+B
D1-B
Pipeline
ADC
12
12
· 500 MHz full power analog bandwidth
VIN+C
VIN-C
D1+C
D1-C
Serial
LVDS
Pipeline
ADC
· Per Channel Core Power Dissipation = 270mW at 65MSPS /
200mW at 50MSPS
VIN+D
VIN-D
Serial
LVDS
D1+D
D1-D
· 1 Vpp – 2 Vpp input voltage range
· +3.0 V supply operation
· Power down mode
Pipeline
ADC
VREF
SENSE
FCO+
FCO-
+
-
0.5 V
APPLICATIONS
REFT
REFB
Ref
Select
Data Rate
Multiplier
DCO+
DCO-
· Digital beam forming systems in ultrasound
· Wireless and wired broadband communications
· Communications test equipment
CLK
AGND
LVDSBIAS
· Radar and satellite imaging sub-systems
Figure 1. Functional Block Diagram
signal a new output byte. Power down is supported and consumes
less than 3mW when enabled.
PRODUCT DESCRIPTION
The AD9229 is a quad 12-bit monolithic sampling analog–to–
digital converter with an on–chip track–and–hold circuit and is
designed for low cost, low power, small size and ease of use. The
product operates up to a 65 MSPS conversion rate and is optimized
for outstanding dynamic performance where a small package size is
critical.
Fabricated on an advanced CMOS process, the AD9229 is available
in a 48-LFCSP package specified over the industrial temperature
range (–40°C to +85°C).
PRODUCT HIGHLIGHTS
1. Four analog-to-digital converters are contained in one small,
space saving package.
2. A Data Clock Output (DCO) is provided which operates up to
390 MHz.
3. The outputs of each ADC are serialized with a maximum data
output rate of 780 Mbps (12-bits x 65 MSPS).
4. The AD9229 operates from a single +3.0 V analog power
supply.
The ADC requires a single+3.0 V power supply and a TTL/CMOS
compatible sample rate clock for full performance operation. No
external reference or driver components are required for many
applications. A separate output power supply pin supports LVDS
compatible serial digital output levels.
The ADC automatically multiplies up the sample rate clock for the
appropriate LVDS serial data rate. An MSB trigger is provided to
Rev. PrF 10/06/2003
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