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AD9230-210EBZ PDF预览

AD9230-210EBZ

更新时间: 2024-10-29 01:07:35
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
33页 1987K
描述
1.8 V Analog-to-Digital Converter

AD9230-210EBZ 数据手册

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12-Bit, 170 MSPS/210 MSPS/250 MSPS,  
1.8 V Analog-to-Digital Converter  
AD9230  
FUNCTIONAL BLOCK DIAGRAM  
FEATURES  
RBIAS  
PWDN  
AGND  
AVDD (1.8V)  
SNR = 64.9 dBFS @ fIN up to 70 MHz @ 250 MSPS  
ENOB of 10.4 @ fIN up to 70 MHz @ 250 MSPS (−1.0 dBFS)  
SFDR = −79 dBc @ fIN up to 70 MHz @ 250 MSPS (−1.0 dBFS)  
Excellent linearity  
REFERENCE  
AD9230  
CML  
DRVDD  
DRGND  
VIN+  
VIN–  
DNL = 0.3 LSB typical  
TRACK-AND-HOLD  
INL = 0.5 LSB typical  
12  
12  
ADC  
12-BIT  
CORE  
OUTPUT  
STAGING  
LVDS  
D11 TO D0  
LVDS at 250 MSPS (ANSI-644 levels)  
700 MHz full power analog bandwidth  
On-chip reference, no external decoupling required  
Integrated input buffer and track-and-hold  
Low power dissipation  
CLK+  
CLK–  
CLOCK  
MANAGEMENT  
OR+  
OR–  
SERIAL PORT  
DCO+  
DCO–  
434 mW @ 250 MSPS—LVDS SDR mode  
400 mW @ 250 MSPS—LVDS DDR mode  
Programmable input voltage range  
1.0 V to 1.5 V, 1.25 V nominal  
RESET SCLK SDIO CSB  
Figure 1. Functional Block Diagram  
1.8 V analog and digital supply operation  
Selectable output data format (offset binary, twos  
complement, Gray code)  
Clock duty cycle stabilizer  
Integrated data capture clock  
APPLICATIONS  
Wireless and wired broadband communications  
Cable reverse path  
Communications test equipment  
Radar and satellite subsystems  
Power amplifier linearization  
GENERAL DESCRIPTION  
PRODUCT HIGHLIGHTS  
The AD9230 is a 12-bit monolithic sampling analog-to-digital  
converter optimized for high performance, low power, and ease  
of use. The product operates at up to a 250 MSPS conversion  
rate and is optimized for outstanding dynamic performance in  
wideband carrier and broadband systems. All necessary  
functions, including a track-and-hold (T/H) and voltage  
reference, are included on the chip to provide a complete signal  
conversion solution.  
1. High Performance—Maintains 64.9 dBFS SNR @ 250 MSPS  
with a 70 MHz input.  
2. Low Power—Consumes only 434 mW @ 250 MSPS.  
3. Ease of Use—LVDS output data and output clock signal  
allow interface to current FPGA technology. The on-chip  
reference and sample and hold provide flexibility in system  
design. Use of a single 1.8 V supply simplifies system  
power supply design.  
The ADC requires a 1.8 V analog voltage supply and a  
differential clock for full performance operation. The digital  
outputs are LVDS (ANSI-644) compatible and support either  
twos complement, offset binary format, or Gray code. A data  
clock output is available for proper output data timing.  
4. Serial Port Control—Standard serial port interface supports  
various product functions, such as data formatting, disabling  
the clock duty cycle stabilizer, power-down, gain adjust,  
and output test pattern generation.  
5. Pin-Compatible Family—10-bit pin-compatible family  
offered as AD9211.  
Fabricated on an advanced CMOS process, the AD9230 is  
available in a 56-lead LFCSP, specified over the industrial  
temperature range (−40°C to +85°C).  
Rev. 0  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
rights of third parties that may result from its use. Specifications subject to change without notice. No  
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.  
Trademarks and registeredtrademarks arethe property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
Fax: 781.461.3113  
www.analog.com  
©2007 Analog Devices, Inc. All rights reserved.  
 

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