Datasheet > AD9129-EBZ

AD9129-EBZ

更新时间： 2024-01-05 12:54:54

品牌	Logo	应用领域
亚德诺 - ADI		转换器
页数	文件大小	规格书
68页	2723K
描述
11-/14-Bit, 5.6 GSPS, RF Digital-to-Analog Converter

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AD9129-EBZ 技术参数

是否无铅：	含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	BGA
包装说明：	LFBGA, BGA160,14X14,32	针数：	160
Reach Compliance Code：	compliant	ECCN代码：	3A001.A.5.B.2
HTS代码：	8542.39.00.01	风险等级：	1.75
最大模拟输出电压：	2.5 V	最小模拟输出电压：	1.5 V
转换器类型：	D/A CONVERTER	输入位码：	BINARY
输入格式：	PARALLEL, WORD	JESD-30 代码：	S-PBGA-B160
JESD-609代码：	e1	长度：	12 mm
湿度敏感等级：	3	标称负供电电压：	-1.5 V
位数：	14	功能数量：	1
端子数量：	160	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	LFBGA	封装等效代码：	BGA160,14X14,32
封装形状：	SQUARE	封装形式：	GRID ARRAY, LOW PROFILE, FINE PITCH
峰值回流温度（摄氏度）：	260	电源：	1.8 V
认证状态：	Not Qualified	座面最大高度：	1.4 mm
标称安定时间 (tstl)：	0.013 µs	子类别：	Other Converters
最大压摆率：	327 mA	标称供电电压：	1.8 V
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子面层：	Tin/Silver/Copper (Sn/Ag/Cu)
端子形式：	BALL	端子节距：	0.8 mm
端子位置：	BOTTOM	处于峰值回流温度下的最长时间：	30
宽度：	12 mm	Base Number Matches：	1

AD9129-EBZ 数据手册

11-/14-Bit, 5.6 GSPS,

RF Digital-to-Analog Converter

Data Sheet

AD9119/AD9129

FEATURES

FUNCTIONAL BLOCK DIAGRAM

RESET

IRQ

I250U VREF

DAC update rate: up to 5.6 GSPS

Direct RF synthesis at 2.8 GSPS data rate

DC to 1.4 GHz in baseband mode

DC to 1.0 GHz in 2× interpolation mode

1.4 GHz to 4.2 GHz in Mix-Mode

AD9129

SDIO

SDO

1.2V

SPI

SCLK

FRM_x

Bypassable 2× interpolation

Excellent dynamic performance

Supports DOCSIS 3.0 wideband ACLR/harmonic performance

8 QAM carriers: ACLR > 65 dBc

(FRAME/

PARITY)

MIX-

NORMAL MODE

BASEBAND

MODE

P0_D[13:0]P,

P0_D[13:0]N

IOUTP

IOUTN

Tx DAC

CORE

DLL

DCI_x

Industry-leading single/multicarrier IF or RF synthesis

4-carrier W-CDMA ACLR at 2457.6 MSPS

2×

_OUT= 900 MHz, ACLR = 71 dBc (baseband mode)

_OUT= 2100 MHz, ACLR = 68 dBc (Mix-Mode)

_OUT= 2700 MHz, ACLR = 67 dBc (Mix-Mode)

P1_D[13:0]P,

P1_D[13:0]N

PLL

Dual-port LVDS and DHSTL data interface

Up to 1.4 GSPS operation

CLOCK

DISTRIBUTION

DCR

DCO_x

Source synchronous DDR clocking with parity bit

Low power: 1.0 W at 2.8 GSPS (1.3 W at 5.6 GSPS)

DACCLK_x

Figure 1.

APPLICATIONS

Broadband communications systems

CMTS/VOD

Wireless infrastructure: W-CDMA, LTE, point-to-point

Instrumentation, automatic test equipment (ATE)

Radars, jammers

GENERAL DESCRIPTION

The AD9119/AD9129 are high performance, 11-/14-bit RF digital-

to-analog converters (DACs) supporting data rates up to 2.8 GSPS.

The DAC core is based on a quad-switch architecture that enables

dual-edge clocking operation, effectively increasing the DAC

update rate to 5.6 GSPS when configured for Mix-Mode™ or 2×

interpolation. The high dynamic range and bandwidth enable

multicarrier generation up to 4.2 GHz.

The AD9119/AD9129 include several features that may further

simplify system integration. A dual-port, source synchronous

LVDS interface simplifies the data interface to a host FPGA/ASIC.

A differential frame/parity bit is also included to monitor the

integrity of the interface. On-chip delay locked loops (DLLs)

are used to optimize timing between different clock domains.

A serial peripheral interface (SPI) is used to configure the

AD9119/AD9129 and monitor the status of readback registers.

The AD9119/AD9129 is manufactured on a 0.18 µm CMOS

process and operates from +1.8 V and −1.5 V supplies. It is

supplied in a 160-ball chip scale package ball grid array.

In baseband mode, wide bandwidth capability combines with high

dynamic range to support from 1 to 158 contiguous carriers for

CATV infrastructure applications. A choice of two optional 2×

interpolation filters is available to simplify the postreconstruction

filter by effectively increasing the DAC update rate by a factor of 2.

In Mix-Mode operation, the AD9119/AD9129 can reconstruct

RF carriers in the second and third Nyquist zone while still

maintaining exceptional dynamic range up to 4.2 GHz. The

high performance NMOS DAC core features a quad-switch

architecture that enables industry-leading direct RF synthesis

performance with minimal loss in output power. The output

current can be programmed over a range of 9.5 mA to 34.4 mA.

PRODUCT HIGHLIGHTS

1. High dynamic range and signal reconstruction bandwidth

support RF signal synthesis of up to 4.2 GHz.

2. Dual-port interface with double data rate (DDR) LVDS

data receivers supports 2800 MSPS maximum conversion rate.

3. Manufactured on a CMOS process; a proprietary switching

technique enhances dynamic performance.

Rev. 0

Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rightsof third parties that may result fromits use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks andregisteredtrademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Technical Support

www.analog.com

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