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AD9142BCPZ PDF预览

AD9142BCPZ

更新时间: 2024-12-01 12:54:15
品牌 Logo 应用领域
亚德诺 - ADI 转换器
页数 文件大小 规格书
65页 1113K
描述
Dual, 16-Bit, 1600 MSPS, TxDAC Digital-to-Analog Converter

AD9142BCPZ 数据手册

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Dual, 16-Bit, 1600 MSPS, TxDAC+  
Digital-to-Analog Converter  
Data Sheet  
AD9142  
FEATURES  
GENERAL DESCRIPTION  
Very small inherent latency variation: <2 DAC clock cycles  
Proprietary low spurious and distortion design  
6-carrier GSM ACLR = 79 dBc at 200 MHz IF  
SFDR > 85 dBc (bandwidth = 300 MHz) at ZIF  
Flexible 16-bit LVDS interface  
Supports word and byte load  
Multiple chip synchronization  
Fixed latency and data generator latency compensation  
Selectable 2×, 4×, 8× interpolation filter  
Low power architecture  
fS/4 power saving coarse mixer  
Input signal power detection  
Emergency stop for downstream analog circuitry  
protection  
FIFO error detection  
The AD9142 is a dual, 16-bit, high dynamic range digital-to-  
analog converter (DAC) that provides a sample rate of 1600 MSPS,  
permitting a multicarrier generation up to the Nyquist frequency.  
The AD9142 TxDAC+® includes features optimized for direct  
conversion transmit applications, including complex digital mod-  
ulation, input signal power detection, and gain, phase, and offset  
compensation. The DAC outputs are optimized to interface  
seamlessly with analog quadrature modulators, such as the  
ADL537x F-MOD series and the ADRF670x series from Analog  
Devices, Inc. A 3-wire serial port interface provides for the pro-  
gramming/readback of many internal parameters. Full-scale  
output current can be programmed over a range of 9 mA to 33 mA.  
The AD9142 is available in a 72-lead LFCSP.  
PRODUCT HIGHLIGHTS  
1. Advanced low spurious and distortion design techniques  
provide high quality synthesis of wideband signals from  
baseband to high intermediate frequencies.  
2. Very small inherent latency variation simplifies both software  
and hardware design in the system. It allows easy multichip  
synchronization for most applications.  
On-chip numeric control oscillator allows carrier placement  
anywhere in the DAC Nyquist bandwidth  
Transmit enable function for extra power saving  
High performance, low noise PLL clock multiplier  
Digital gain and phase adjustment for sideband suppression  
Digital inverse sinc filter  
3. New low power architecture improves power efficiency  
(mW/MHz/channel) by 30%.  
4. Input signal power and FIFO error detection simplify  
designs for downstream analog circuitry protection.  
5. Programmable transmit enable function allows easy design  
balance between power consumption and wakeup time.  
Supports single DAC mode  
Low power: 2.0 W at 1.6 GSPS, 1.7 W at 1.25 GSPS, full  
operating conditions  
72-lead LFCSP  
APPLICATIONS  
Wireless communications: 3G/4G and MC-GSM base stations,  
wideband repeaters, software defined radios  
Wideband communications: point-to-point, LMDS/MMDS  
Transmit diversity/MIMO  
Instrumentation  
Automated test equipment  
Rev. 0  
Document Feedback  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
rightsof third parties that may result fromits use. Specifications subject to change without notice. No  
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.  
Trademarks andregisteredtrademarks are the property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
©2012 Analog Devices, Inc. All rights reserved.  
Technical Support  
www.analog.com  
 
 
 
 

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