Dual, 11-/16-Bit, 2.8 GSPS, TxDAC+®
Digital-to-Analog Converters
Data Sheet
AD9135/AD9136
FEATURES
TYPICAL APPLICATION CIRCUIT
QUAD MOD
LPF
Support input data rate >2 GSPS
Proprietary low spurious and distortion design
SFDR = 82 dBc at dc IF, −9 dBFS
SYSREF±
ADRF6720
DAC
Flexible 8-lane JESD204B interface
Multiple chip synchronization
0°/90° PHASE
SHIFTER
RF OUTPUT
JESD204B
Fixed latency
DAC
SYNCOUT0±
SYNCOUT1±
Data generator latency compensation
Selectable 1×, 2×, 4×, or 8× interpolation filter
Low power architecture
AD9135/
AD9136
LO_IN
MOD_SPI
CLK± DAC
SPI
Transmit enable function allows extra power saving and
instant control of the output status
High performance, low noise phase-locked loop (PLL) clock
multiplier
Figure 1.
Digital inverse sinc filter
Low power: 1.42 W at 1.6 GSPS full operating conditions
88-lead LFCSP with exposed pad
APPLICATIONS
Wireless communications
3G/4G W-CDMA base stations
Wideband repeaters
Software defined radios
Wideband communications
Point to point
Local multipoint distribution service (LMDS) and
multichannel multipoint distribution service (MMDS)
Transmit diversity, multiple input/multiple output (MIMO)
Instrumentation
Automated test equipment
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The AD9135/AD9136 are dual, 11-/16-bit, high dynamic range
digital-to-analog converters (DACs) that provide a maximum
sample rate of 2800 MSPS, permitting a multicarrier generation
over a very wide bandwidth. The DAC outputs are optimized to
interface seamlessly with the ADRF6720, as well as other analog
quadrature modulators (AQMs) from Analog Devices, Inc. An
optional 3-wire or 4-wire serial port interface (SPI) provides for
programming/readback of many internal parameters. The full-
scale output current can be programmed over a typical range of
13.9 mA to 27.0 mA. The AD9135/AD9136 are available in an
88-lead LFCSP.
1. Greater than 2 GHz, ultrawide complex signal bandwidth
enables emerging wideband and multiband wireless
applications.
2. Advanced low spurious and distortion design techniques
provide high quality synthesis of wideband signals from
baseband to high intermediate frequencies.
3. JESD204B Subclass 1 support simplifies multichip
synchronization in software and hardware design.
4. Fewer pins for data interface width with a serializer/
deserializer (SERDES) JESD204B eight-lane interface.
5. Programmable transmit enable function allows easy design
balance between power consumption and wake-up time.
6. Small package size with 12 mm × 12 mm footprint.
Rev. C
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