AD8343
APPLICATIONS
are obtained through the use of 1:1 transmission line baluns.
The differential input and output matching networks are
designed between the balun and the I/O pins of the AD8343.
The local oscillator signal at a level of –12 dBm to –3 dBm is
brought in through a third 1:1 balun.
DOWNCONVERTING MIXER
A typical downconversion application is shown in Figure 69
with the AD8343 connected as a receive mixer. The input
single-ended-to-differential conversion is obtained through
the use of a 1:1 transmission line balun. The input matching
network is positioned between the balun and the input pins,
while the output is taken directly from a 4:1 impedance ratio
(2:1 turns ratio) transformer. The local oscillator signal at a level
of –12 dBm to –3 dBm is brought in through a second 1:1 balun.
R1A and R1B set the core bias current of 18 mA per side. Z1,
Z2A, and Z2B comprise a typical input matching network
designed to match the AD8343s differential input impedance
to the differential output impedance of the balun. It is assumed
for this example that the input frequency is low and that the
magnitude of the device’s input impedance is therefore much
smaller than the bias resistor values, allowing the input bias
inductors to be eliminated with very little penalty in gain or
noise performance.
V
POS
4.71Ω
5
1
7
8
11 14
V
POS
VPOS
AD8343
COMM
0.1µF
DCPL
4:1
In this example, the output signal is taken via a differential
matching network comprising Z3 and Z4A/Z4B, then
through the 1:1 balun and dc blocking capacitors to the
single-ended output.
4
6
13
12
IF
OUT
BIAS
FB
PWDN
FERRITE BEAD
1:1
LOIP
LOIM
LO IN
–10dBm
10
9
The output frequency is assumed to be high enough that
conjugate matching to the output of the AD8343 is desirable,
so the goal of the matching network is to provide a conjugate
match between the device’s output and the differential input of
the output balun.
INPP
Z1
INPM
3
2
L1
L1
B
A
R1
R1
B
68Ω
A
68Ω
˜
˜
Z2
Z2
B
1:1
A
R
FIN
This circuit uses shunt feed to provide collector bias for the
transistors because the output balun in this circuit has no
convenient center-tap. The ferrite beads, in series with the
output’s bias inductors, provide some small degree of damping
to ease the common-mode stability problem. Unfortunately, this
type of output balun can present a common-mode load that
enters the region of output instability, so most of the burden of
avoiding overt instability falls on the input circuit, presenting an
inductive common-mode termination over as broad a band of
frequencies as possible.
Figure 69. Typical Downconversion Application
R1A and R1B set the core bias current of 18.5 mA per side. L1A
and L1B provide the RF choking required to avoid shunting the
signal. Z1, Z2A, and Z2B comprise a typical input matching
network that is designed to match the AD8343s differential
input impedance to the differential output impedance of the
balun.
The IF output is taken through a 4:1 (impedance ratio) trans-
former that reflects a 200 Ω differential load to the collectors.
This output coupling arrangement is reasonably broadband,
although in some cases the user might want to consider adding
a resonator tank circuit between the collectors to provide a
measure of IF selectivity. The ferrite bead (FB), in series with
the output transformer’s center tap, addresses the common-
mode stability concern.
The PWDN pin is shown as tied to GND, enabling the mixer.
The DCPL pin must be bypassed to GND with about 0.1 μF to
bypass noise from the internal bias circuit.
V
POS
0.1µF
V
POS
5
1
7
8
11 14
FB
VPOS
AD8343
COMM
0.1µF
DCPL
4
6
Z4
Z4
13
12
RF
A
OUT
BIAS
In this circuit, the PWDN pin is shown connected to GND,
enabling the mixer. In order to enter power-down mode and
conserve power, the PWDN pin must be taken within 500 mV
of VPOS. The DCPL pin is bypassed to GND with about 0.1 μF.
Failure to do so results in a higher noise level at the output of
the device.
Z3
PWDN
B
0.1µF
0.1µF
LOIP
LOIM
FB
10
9
LO IN
LO
DRIVER
V
POS
INPP
INPM
3
2
R
FIN
Z2
A
Z1
UPCONVERTING MIXER
Z2
B
R1
R1
B
A
A typical upconversion application is shown in Figure 70. Both
the input and output single-ended-to-differential conversions
Figure 70. Typical Upconversion Application
Rev. B | Page 26 of 32
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