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AD8342-EVAL

更新时间: 2024-01-20 07:57:04
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
20页 683K
描述
Active Receive Mixer LF to 500 MHz

AD8342-EVAL 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:ActiveReach Compliance Code:unknown
风险等级:5.64Is Samacsys:N
特性阻抗:50 Ω构造:COMPONENT
最大输入功率 (CW):12 dBmJESD-609代码:e3
最大工作频率:2400 MHz最小工作频率:50 MHz
最高工作温度:85 °C最低工作温度:-40 °C
射频/微波设备类型:DOUBLE BALANCED端子面层:MATTE TIN
Base Number Matches:1

AD8342-EVAL 数据手册

 浏览型号AD8342-EVAL的Datasheet PDF文件第12页浏览型号AD8342-EVAL的Datasheet PDF文件第13页浏览型号AD8342-EVAL的Datasheet PDF文件第14页浏览型号AD8342-EVAL的Datasheet PDF文件第16页浏览型号AD8342-EVAL的Datasheet PDF文件第17页浏览型号AD8342-EVAL的Datasheet PDF文件第18页 
AD8342  
AC INTERFACES  
The AD8342 is designed to downconvert radio frequencies (RF)  
to lower intermediate frequencies (IF) using a high or low-side  
local oscillator (LO). The LO is injected into the mixer core at a  
frequency higher or lower than the desired input RF. The  
difference between the LO and the RF , fLO − fRF, (high side) or  
fRF − fLO (low side) is the intermediate frequency, fIF. In addition  
to the desired RF signal, an RF image is downconverted to the  
desired IF frequency. The image frequency is at fLO + fIF when  
driven with a high side LO . When using a broadband load, the  
conversion gain of the AD8342 is nearly constant over the  
specified RF input band (see Figure 3).  
Table 4. Dynamic Performance for Various Input Networks  
Input  
Network  
50 Ω  
Shunt  
100 Ω  
Shunt  
500 Ω  
Shunt  
Matched  
(Fig. 40)  
Gain (dB)  
IIP3 (dBm)  
P1dB (dBm)  
NF (dB)  
0.66  
25.4  
10.8  
14  
3.5  
22.9  
8.4  
5.3  
20. 6  
6.3  
9.3  
18.5  
2.3  
12.5  
10.2  
10.5  
The RF port can also be matched using an LC circuit, as shown  
in Figure 42.  
50  
100nH  
(1000 + j0) Ω  
The AD8342 is designed to operate over a broad frequency  
range. It is essential to ac-couple RF and LO ports to prevent dc  
offsets from skewing the mixer core in an asymmetrical man-  
ner, potentially degrading noise figure and linearity.  
Z
MAIN  
= 50  
O
f
= 250MHz  
3.6pF  
1kΩ  
Z
L
Figure 42. Matching Circuit  
The RF input of the AD8342 is high impedance, 1 kΩ across the  
frequency range shown in Figure 41. The input capacitance  
decreases with frequency due to package parasitics.  
Impedance transformations of greater than 10:1 result in a  
higher Q circuit and thus a narrow RF input bandwidth. A 1 kΩ  
resistor is placed across the RF input of the device in parallel  
with the device internal input impedance, creating a 500 Ω load.  
This impedance is matched to as close as possible to 50 Ω for  
the source, with standard components using a shunt C, series L  
matching circuit (see Figure 43).  
2.00  
1.75  
1.50  
1.25  
1.00  
0.75  
0.50  
0.25  
0
1.00  
0.75  
0.50  
0.25  
0
50.0  
25.0  
100.0  
Q = 3.0  
200.0  
10.0  
500.0  
0
100M 200M 300M 400M 500M 600M 700M 800M 900M 1G  
FREQUENCY (Hz)  
2
1
4
Figure 41. RF Input Impedance  
500.0  
200.0  
100.0  
The matching or termination used at the RF input of the  
AD8342 has a direct effect on its dynamic range. The charac-  
terization circuit, as well as the evaluation board, uses a 100 Ω  
resistor to terminate the RF port. This termination resistor in  
shunt with the input stage results in a return loss of better than  
−10 dBm (relative to 50 Ω). Table 4 shows gain, IP3, P1dB, and  
noise figure for four different input networks. This data was  
measured at an RF frequency of 250 MHz and at an LO  
frequency of 300 MHz.  
3
50.0  
25.0  
10.0  
Point 1(1000.0 + j0.0)Ω Q = 0.0 at 250.000 MHz  
Point 2(500.0 + j0.0)Ω Q = 0.0 at 250.000 MHz  
Point 3(55.6 − j157.2)Ω Q = 2.8 at 250.000 MHz  
Point 4(55.6 − j0.1)Ω Q = 0.0 at 250.000 MHz  
Figure 43. LC Matching Example  
Rev. 0 | Page 15 of 20  
 
 
 
 

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