2-Channel, 2.35 V to 5.25 V,
1 MSPS, 10-/12-Bit ADCs
AD7912/AD7922
FUNCTIONAL BLOCK DIAGRAM
FEATURES
V
DD
Fast throughput rate: 1 MSPS
Specified for VDD of 2.35 V to 5.25 V
Low power:
4.8 mW typ at 1 MSPS with 3 V supplies
15.5mW typ at 1 MSPS with 5 V supplies
Wide input bandwidth:
V
V
IN0
IN1
10-/12-BIT
SUCCESSIVE
APPROXIMATION
ADC
T/H
MUX
71 dB minimum SNR at 100 kHz input frequency
Flexible power/serial clock speed management
No pipeline delays
SCLK
CS
High speed serial interface:
AD7912/AD7922
CONTROL LOGIC
SPI®/QSPI™/MICROWIRE™/DSP compatible
Standby mode: 1 µA maximum
Daisy-chain mode
DOUT
DIN
8-lead TSOT package
GND
8-lead MSOP package
Figure 1.
APPLICATIONS
Several AD7912/AD7922 can be connected together in a daisy
chain. The AD7912/AD7922 feature a daisy-chain mode that
allows the user to read the conversion results from the ADCs
contained in the chain. The AD7912/AD7922 use advanced
design techniques to achieve very low power dissipation at high
throughput rates. The reference for the part is taken internally
from VDD, thereby allowing the widest dynamic input range to
the ADC.
Battery-powered systems:
Personal digital assistants
Medical instruments
Mobile communications
Instrumentation and control systems
Data acquisition systems
High speed modems
Optical sensors
PRODUCT HIGHLIGHTS
GENERAL DESCRIPTION
1. 2-channel, 1 MSPS, 10-/12-bit ADCs in TSOT package.
2. High throughput with low power consumption.
3. Flexible power/serial clock speed management.
The conversion rate is determined by the serial clock. The
parts also feature a power-down mode to maximize power
efficiency at lower throughput rates. Average power
consumption is reduced when the power-down mode is
used while not converting. Current consumption is 1 µA
maximum and 50 nA typically when in power-down mode.
4. Daisy-chain mode.
The AD7912/AD79221 are 10-bit and 12-bit, high speed, low
power, 2-channel successive approximation ADCs, respectively.
The parts operate from a single 2.35 V to 5.25 V power supply
and feature throughput rates of up to 1 MSPS. The parts contain
a low noise, wide bandwidth track-and-hold amplifier, which
can handle input frequencies in excess of 6 MHz.
The conversion process and data acquisition are controlled
CS
using
and the serial clock, allowing the devices to interface
with microprocessors or DSPs. The conversion rate is
determined by the SCLK signal. The input signal is sampled on
5. No pipeline delay.
The parts feature a standard successive approximation ADC
CS
the falling edge of
and the conversion is also initiated at this
CS
with accurate control of the sampling instant via a
and once-off conversion control.
input
point. The channel to be converted is selected through the DIN
CS
pin, and the mode of operation is controlled by . The serial
data stream from the DOUT pin has a channel identifier bit and
mode identifier bit, which provide information about the
converted channel and the current mode of operation.
1 Protected by U.S. Patent Number 6,681,332.
Rev. 0
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