4-Channel, 200 kSPS 12-Bit ADC
with Sequencer in 16-Lead TSSOP
AD7923-EP
Enhanced Product
clock to control the conversion. The conversion time can be as
short as 800 ns with a 20 MHz SCLK.
FEATURES
Fast throughput rate: 200 kSPS
Specified for AVDD of 2.7 V to 5.25 V
Low power
Additional application and technical information can be found
in the AD7923 data sheet.
3.6 mW max at 200 kSPS with 3 V supply
7.5 mW max at 200 kSPS with 5 V supply
4 (single-ended) inputs with sequencer
Wide input bandwidth
FUNCTIONAL BLOCK DIAGRAM
AV
DD
REF
IN
70 dB min SNR at 50 kHz input frequency
Flexible power/serial clock speed management
No pipeline delays
High speed serial interface SPI®-/QSPI™-/
MICROWIRE™-/DSP-compatible
Shutdown mode: 0.5 µA max
V
0
IN
•
•
•
•
•
•
•
•
•
•
•
•
T/H
12-BIT
SUCCESSIVE
APPROXIMATION
ADC
INPUT
MUX
16-lead TSSOP package
Support defense and aerospace applications (AQEC)
Military temperature range (−55°C to +125°C)
Controlled manufacturing baseline
One assembly/test site
•
V
3
IN
SCLK
DOUT
DIN
CONTROL LOGIC
SEQUENCER
One fabrication site
Enhanced product change notification
Qualification data available on request
CS
AD7923-EP
V
DRIVE
GENERAL DESCRIPTION
GND
Figure 1.
The AD7923-EP is a 12-bit, high speed, low power, 4-channel,
successive approximation (SAR) ADC. It operates from a single
2.7 V to 5.25 V power supply and features throughput rates up to
200 kSPS. It contains a low noise, wide bandwidth track-and-hold
amplifier that can handle input frequencies in excess of 8 MHz.
PRODUCT HIGHLIGHTS
1. High Throughput with Low Power Consumption.
The AD7923-EP offers up to 200 kSPS throughput rates.
At the maximum throughput rate with 3 V supplies, the
AD7923-EP dissipates just 3.6 mW of power.
The conversion process and data acquisition are controlled by
2. Four Single-Ended Inputs with a Channel Sequencer.
3. Single-Supply Operation with VDRIVE Function.
The VDRIVE function allows the serial interface to connect
directly to either 3 V or 5 V processor systems independent
CS
and the serial clock, allowing the device to easily interface
with microprocessors or DSPs. The input signal is sampled on
CS
the falling edge of ; the conversion is also initiated at this point.
The AD7923-EP uses advanced design techniques to achieve
very low power dissipation at maximum throughput rates. At
maximum throughput rates, it consumes 1.2 mA maximum
with 3 V supplies and 1.5 mA maximum with 5 V supplies.
of AVDD
.
4. Flexible Power/Serial Clock Speed Management.
The conversion rate is determined by the serial clock,
allowing the conversion time to be reduced through the
serial clock speed increase. The part also features various
shutdown modes to maximize power efficiency at lower
throughput rates. Current consumption is 0.5 µA maximum
when in full shutdown.
Through the configuration of the control register, the analog
input range can be selected as 0 V to REFIN or 0 V to 2 × REFIN,
with either straight binary or twos complement output coding.
The AD7923-EP features four single-ended analog inputs with a
channel sequencer to allow a preprogrammed selection of
channels to be converted sequentially.
5. No Pipeline Delay.
The part features a SAR ADC with accurate control of the
CS
sampling instant via a
control.
input and once off conversion
The conversion time for the AD7923-EP is determined by the
serial clock, SCLK, frequency, since this is used as the master
Rev. 0
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rightsof third parties that may result fromits use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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