4-Channel, 200 kSPS 12-Bit ADC
with Sequencer in 16-Lead TSSOP
AD7923
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Fast throughput rate: 200 kSPS
Specified for AVDD of 2.7 V to 5.25 V
Low power
AV
DD
REF
IN
3.6 mW max at 200 kSPS with 3 V supply
7.5 mW max at 200 kSPS with 5 V supply
4 (single-ended) inputs with sequencer
Wide input bandwidth
70 dB Min SNR at 50 kHz input frequency
Flexible power/serial clock speed management
No pipeline delays
High speed serial interface SPI®-/QSPITM-/
MICROWIRETM-/DSP-compatible
Shutdown mode: 0.5 μA max
V
0
IN
•
•
•
•
•
•
•
•
•
•
•
•
•
T/H
12-BIT
SUCCESSIVE
APPROXIMATION
ADC
I/P
MUX
V
3
IN
SCLK
DOUT
DIN
16-lead TSSOP package
Qualified for automotive applications
CONTROL LOGIC
SEQUENCER
CS
AD7923
GENERAL DESCRIPTION
V
DRIVE
The AD7923 is a 12-bit, high speed, low power, 4-channel, suc-
cessive approximation (SAR) ADC. It operates from a single
2.7 V to 5.25 V power supply and features throughput rates up to
200 kSPS. It contains a low noise, wide bandwidth track-and-hold
amplifier that can handle input frequencies in excess of 8 MHz.
GND
Figure 1.
PRODUCT HIGHLIGHTS
1. High Throughput with Low Power Consumption.
The AD7923 offers up to 200 kSPS throughput rates. At the
maximum throughput rate with 3 V supplies, the AD7923
dissipates just 3.6 mW of power.
The conversion process and data acquisition are controlled by
CS
and the serial clock, allowing the device to easily interface
with microprocessors or DSPs. The input signal is sampled on
2. Four Single-Ended Inputs with a Channel Sequencer.
CS
the falling edge of ; the conversion is also initiated at this
3. Single-Supply Operation with VDRIVE Function.
The VDRIVE function allows the serial interface to connect
directly to either 3 V or 5 V processor systems independent
point.
The AD7923 uses advanced design techniques to achieve very
low power dissipation at maximum throughput rates. At
maximum throughput rates, it consumes 1.2 mA maximum
with 3 V supplies and 1.5 mA maximum with 5 V supplies.
of AVDD
.
4. Flexible Power/Serial Clock Speed Management.
The conversion rate is determined by the serial clock,
allowing the conversion time to be reduced through the
serial clock speed increase. The part also features various
shutdown modes to maximize power efficiency at lower
throughput rates. Current consumption is 0.5 μA
maximum when in full shutdown.
Through the configuration of the control register, the analog
input range can be selected as 0 V to REFIN or 0 V to 2 × REFIN,
with either straight binary or twos complement output coding.
The AD7923 features four single-ended analog inputs with a
channel sequencer to allow a preprogrammed selection of
channels to be converted sequentially.
5. No Pipeline Delay.
The part features a SAR ADC with accurate control of the
The conversion time for the AD7923 is determined by the serial
clock, SCLK, frequency, since this is used as the master clock to
control the conversion. The conversion time can be as short as
800 ns with a 20 MHz SCLK.
CS
sampling instant via a
control.
input and once off conversion
Rev. C
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