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AD7921 PDF预览

AD7921

更新时间: 2024-11-23 22:49:59
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亚德诺 - ADI /
页数 文件大小 规格书
28页 312K
描述
2-Channel, 2.35 V to 5.25 V 250 kSPS, 10-/12-Bit ADCs

AD7921 数据手册

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2-Channel, 2.35 V to 5.25 V  
250 kSPS, 10-/12-Bit ADCs  
AD7911/AD7921  
FUNCTIONAL BLOCK DIAGRAM  
FEATURES  
V
DD  
Fast throughput rate: 250 kSPS  
Specified for VDD of 2.35 V to 5.25 V  
Low power:  
4 mW typ at 250 kSPS with 3 V supplies  
13.5 mW typ at 250 kSPS with 5 V supplies  
Wide input bandwidth:  
V
V
IN0  
IN1  
10-/12-BIT  
SUCCESSIVE  
APPROXIMATION  
ADC  
T/H  
MUX  
71 dB minimum SNR at 100 kHz input frequency  
Flexible power/serial clock speed management  
No pipeline delays  
SCLK  
CS  
High speed serial interface:  
AD7911/AD7921  
CONTROL LOGIC  
SPI®/QSPI™/MICROWIRE™/DSP compatible  
Standby mode: 1 µA maximum  
8-lead TSOT package  
DOUT  
DIN  
8-lead MSOP package  
GND  
APPLICATIONS  
Figure 1.  
Battery-powered systems:  
Personal digital assistants  
Medical instruments  
Mobile communications  
Instrumentation and control systems  
Data acquisition systems  
High speed modems  
The AD7911/AD7921 use advanced design techniques to  
achieve very low power dissipation at high throughput rates.  
The reference for the part is taken internally from VDD, thereby  
allowing the widest dynamic input range to the ADC. The  
analog input range for the part, therefore, is 0 to VDD. The  
conversion rate is determined by the SCLK signal.  
Optical sensors  
GENERAL DESCRIPTION  
PRODUCT HIGHLIGHTS  
The AD7911/AD79211 are 10-bit and 12-bit, high speed, low  
power, 2-channel successive approximation ADCs, respectively.  
The parts operate from a single 2.35 V to 5.25 V power supply  
and feature throughput rates of up to 250 kSPS. The parts  
contain a low noise, wide bandwidth track-and-hold amplifier,  
which can handle input frequencies in excess of 6 MHz. The  
1. 2-channel, 250 kSPS, 10-/12-bit ADCs in TSOT package.  
2. Low power consumption.  
3. Flexible power/serial clock speed management.  
The conversion rate is determined by the serial clock;  
conversion time is reduced when the serial clock speed is  
increased. The parts also feature a power-down mode to  
maximize power efficiency at lower throughput rates.  
Average power consumption is reduced when the power-  
down mode is used while not converting. Current  
consumption is 1 µA maximum and 50 nA typically when  
in power-down mode.  
CS  
conversion process and data acquisition are controlled using  
and the serial clock, allowing the devices to interface with  
microprocessors or DSPs. The input signal is sampled on the  
CS  
falling edge of , and the conversion is also initiated at this  
point. There are no pipeline delays associated with the part.  
4. Reference derived from the power supply.  
5. No pipeline delay.  
The channel to be converted is selected through the DIN pin,  
The parts feature a standard successive approximation  
CS  
and the mode of operation is controlled by . The serial data  
CS  
ADC with accurate control of the sampling instant via a  
input and once-off conversion control.  
stream from the DOUT pin has a channel identifier bit, which  
provides information about the converted channel.  
1 Protected by U.S. Patent Number 6,681,332.  
Rev. 0  
Information furnished by Analog Devices is believed to be accurate and reliable.  
However, no responsibility is assumed by Analog Devices for its use, nor for any  
infringements of patents or other rights of third parties that may result from its use.  
Specifications subject to change without notice. No license is granted by implication  
or otherwise under any patent or patent rights of Analog Devices. Trademarks and  
registered trademarks are the property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
Fax: 781.326.8703  
www.analog.com  
© 2004 Analog Devices, Inc. All rights reserved.  

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