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AD7716 PDF预览

AD7716

更新时间: 2024-09-16 22:49:59
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
16页 432K
描述
LC2MOS 22-Bit Data Acquisition System

AD7716 数据手册

 浏览型号AD7716的Datasheet PDF文件第2页浏览型号AD7716的Datasheet PDF文件第3页浏览型号AD7716的Datasheet PDF文件第4页浏览型号AD7716的Datasheet PDF文件第5页浏览型号AD7716的Datasheet PDF文件第6页浏览型号AD7716的Datasheet PDF文件第7页 
LC2MOS  
a
22-Bit Data Acquisition System  
AD7716  
FUNCTIONAL BLOCK DIAGRAM  
FEATURES  
22-Bit Sigma-Delta ADC  
AV  
AV  
SS  
DV  
RESET  
CLKIN CLKOUT  
A0 A1 A2  
DD  
DD  
Dynamic Range of 105 dB (146 Hz Input)  
؎0.003% Integral Nonlinearity  
On-Chip Low-Pass Digital Filter  
Cutoff Programmable from 584 Hz to 36.5 Hz  
Linear Phase Response  
AD7716  
CLOCK  
GENERATION  
LOW PASS  
DIGITAL  
FILTER  
ANALOG  
MODULATOR  
A
A
1
2
3
4
IN  
MODE  
CONTROL  
CASCIN  
CASCOUT  
Five Line Serial I/O  
LOGIC  
Twos Complement Coding  
Easy Interface to DSPs and Microcomputers  
Software Control of Filter Cutoff  
؎5 V Supply  
LOW PASS  
DIGITAL  
FILTER  
ANALOG  
MODULATOR  
IN  
RFS  
OUTPUT  
SHIFT  
SDATA  
REGISTER  
SCLK  
LOW PASS  
DIGITAL  
FILTER  
ANALOG  
MODULATOR  
Low Power Operation: 50 mW  
A
IN  
DRDY  
APPLICATIONS  
Biomedical Data Acquisition  
ECG Machines  
LOW PASS  
DIGITAL  
FILTER  
ANALOG  
MODULATOR  
CONTROL  
REGISTER  
A
IN  
TFS  
EEG Machines  
Process Control  
High Accuracy Instrumentation  
Seismic Systems  
V
D
1
D
2
D
1
AGND DGND  
REF  
OUT  
OUT  
IN  
GENERAL DESCRIPTION  
There are 22 bits of data corresponding to the analog input.  
Two bits contain the channel address and 3 bits are the device  
address. Thus, each channel in a 32-channel system would have  
a discrete 5-bit address. The device also has a CASCOUT pin  
and a CASCIN pin that allow simple networking of multiple  
devices.  
The AD7716 is a signal processing block for data acquisition  
systems. It is capable of processing four channels with band-  
widths of up to 584 Hz. Resolution is 22 bits and the usable  
dynamic range varies from 111 dB with an input bandwidth of  
36.5 Hz to 99 dB with an input bandwidth of 584 Hz.  
The device consists of four separate A/D converter channels that  
are implemented using sigma-delta technology. Sigma-delta  
ADCs include on-chip digital filtering and, thus, the system  
filtering requirements are eased.  
The on-chip control register is programmed using the SCLK,  
SDATA and TFS pins. Three bits of the Control Register set  
the digital filter cutoff frequency for the device. Selectable fre-  
quencies are 584 Hz, 292 Hz, 146 Hz, 73 Hz and 36.5 Hz. A  
further 2 bits appear as outputs DOUT1 and DOUT2 and can be  
used for controlling calibration at the front end. The device is  
available in a 44-pin PQFP (Plastic Quad Flatpack) and 44-pin  
PLCC.  
Three address pins program the device address. This allows a  
data acquisition system with up to 32 channels to be set up in a  
simple fashion. The output word from the device contains 32  
bits of data. One bit is determined by the state of the DIN1 in-  
put and may be used, for example, in an ECG system with an  
external pacemaker detect circuit to indicate that the output  
word is invalid because of the presence of a pacemaker pulse.  
REV. A  
Information furnished by Analog Devices is believed to be accurate and  
reliable. However, no responsibility is assumed by Analog Devices for its  
use, nor for any infringements of patents or other rights of third parties  
which may result from its use. No license is granted by implication or  
otherwise under any patent or patent rights of Analog Devices.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 617/329-4700  
Fax: 617/326-8703  

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