Dual, Simultaneous Sampling, 16-Bit/14-Bit
SAR ADCs, Differential Inputs
Data Sheet
AD7380/AD7381
FEATURES
FUNCTIONAL BLOCK DIAGRAM
V
V
LOGIC
CC
16-bit/14-bit ADC family
Dual simultaneous sampling
Fully differential analog inputs
4 MSPS throughput conversion rate
SNR (typical)
A
A
A+
IN
OVER-
SAMPLING
ADC A
SDOA
A–
IN
REFIO
REFCAP
92.5 dB, VREF = 3.3 V external at AD7380 (16-bit)
85.4 dB, VREF = 3.3 V external at AD7381 (14-bit)
On-chip oversampling function
Resolution boost function
SNR 102.8 dB (typical) with ×32 OSR
INL (maximum)
OSC
GND
REF
LDO
SCLK
SDI
CONTROL
LOGIC
REFCAP
CS
A
A
B+
IN
OVER-
ADC B
GND
SDOB/ALERT
SAMPLING
B–
IN
2.0 LSBs at 16-bit
1.0 LSB at 14-bit
AD7380/AD7381
2.5 V internal reference at 10 ppm/°C
High speed serial interface
−40°C to +125°C operation
16-lead LFCSP, 3 mm × 3 mm
Wide common-mode range
Alert function
Figure 1.
APPLICATIONS
Motor control position feedback
Motor control current sense
Sonar
Power quality
Data acquisition systems
EDFA applications
I and Q demodulation
GENERAL DESCRIPTION
The AD7380/AD7381 are a 16-bit and 14-bit pin-compatible
family of dual simultaneous sampling, high speed, low power,
successive approximation register (SAR) analog-to-digital
converters (ADC) that operate from a 3.0 V to 3.6 V power supply
and feature throughput rates up to 4 MSPS. The analog input
type is differential, accepts a wide common-mode input voltage,
The AD7380/AD7381 are available in a 16-lead lead frame chip
scale package (LFCSP) with operation specified from −40°C to
+125°C.
PRODUCT HIGHLIGHTS
1. Dual simultaneous sampling and conversion with two
complete ADC functions.
2. Pin-compatible product family.
CS
and is sampled and converted on the falling edge of
.
Integrated on-chip oversampling blocks improve dynamic range
and reduce noise at lower bandwidths. A buffered internal 2.5 V
reference is included. Alternatively, an external reference up to
3.3 V can be used.
3. High 4 MSPS throughput rate.
4. Space saving 3 mm × 3 mm LFCSP package.
5. Integrated oversampling block to increase dynamic range,
reduce noise, and reduce SCLK speed requirements.
6. Differential analog inputs with wide common-mode range.
7. Small sampling capacitor reduces amplifier drive burden.
The conversion process and data acquisition use standard
control inputs allowing easy interfacing to microprocessors or
digital signal processors (DSPs). It is compatible with 1.8 V,
2.5 V, and 3.3 V interfaces, using the separate logic supply.
Rev. 0
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