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AD73560BB-40 PDF预览

AD73560BB-40

更新时间： 2024-01-21 17:05:54
品牌 Logo 应用领域
亚德诺 - ADI 时钟外围集成电路
页数 文件大小 规格书
39页 641K
描述
IC 0-BIT, 16.384 MHz, OTHER DSP, PBGA119, PLASTIC, BGA-119, Digital Signal Processor

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中文翻译

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AD73560BB-40 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：BGA包装说明：PLASTIC, BGA-119
针数：119Reach Compliance Code：not_compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.92地址总线宽度：
桶式移位器：YES位大小：16
边界扫描：NO最大时钟频率：16.384 MHz
外部数据总线宽度：格式：FIXED POINT
内部总线架构：MULTIPLEJESD-30 代码：R-PBGA-B119
JESD-609代码：e0长度：22 mm
低功率模式：YES端子数量：119
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：BGA
封装等效代码：BGA119,7X17,50封装形状：RECTANGULAR
封装形式：GRID ARRAY峰值回流温度（摄氏度）：NOT SPECIFIED
电源：3.3 V认证状态：Not Qualified
RAM（字数）：8192座面最大高度：2.27 mm
子类别：Digital Signal Processors最大供电电压：3.3 V
最小供电电压：2.7 V标称供电电压：3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：BALL端子节距：1.27 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：14 mmuPs/uCs/外围集成电路类型：DIGITAL SIGNAL PROCESSOR, OTHER
Base Number Matches：1

AD73560BB-40 数据手册

 浏览型号AD73560BB-40的Datasheet PDF文件第7页浏览型号AD73560BB-40的Datasheet PDF文件第8页浏览型号AD73560BB-40的Datasheet PDF文件第9页浏览型号AD73560BB-40的Datasheet PDF文件第11页浏览型号AD73560BB-40的Datasheet PDF文件第12页浏览型号AD73560BB-40的Datasheet PDF文件第13页 
AD73560  
VINP1  
VINN1  
ANALOG  
⌺-⌬  
MODULATOR  
SIGNAL  
CONDITIONING  
0/38dB  
PGA  
DECIMATOR  
DECIMATOR  
DECIMATOR  
SDI  
SDIFS  
SCLK2  
VINP2  
VINN2  
ANALOG  
⌺-⌬  
MODULATOR  
SIGNAL  
CONDITIONING  
0/38dB  
PGA  
VINP3  
VINN3  
ANALOG  
⌺-⌬  
MODULATOR  
SIGNAL  
CONDITIONING  
0/38dB  
PGA  
ARESET  
AMCLK  
SE  
REFERENCE  
REFCAP  
REFOUT  
SERIAL  
I/O  
PORT  
AD73360  
VINP4  
VINN4  
ANALOG  
⌺-⌬  
MODULATOR  
SIGNAL  
CONDITIONING  
0/38dB  
PGA  
DECIMATOR  
DECIMATOR  
DECIMATOR  
VINP5  
VINN5  
ANALOG  
SIGNAL  
CONDITIONING  
0/38dB  
PGA  
-
⌺ ⌬  
MODULATOR  
SDO  
SDOFS  
VINP6  
VINN6  
ANALOG  
⌺-⌬  
MODULATOR  
SIGNAL  
CONDITIONING  
0/38dB  
PGA  
Figure 2. Function Block Diagram of Analog Front End  
amplifiers in the circuit. T he input signal level to the  
sigma-delta modulator should not exceed the maximum  
input voltage permitted.  
F UNC T IO NAL D SE C RIP T IO N - AF E  
T he PGA gain is set by bits IGS0, IGS1 and IGS2 in  
control Registers D, E and F.  
E n cod er C h a n n el  
Each encoder channel consists of a signal conditioner, a  
switched capacitor PGA and a sigma-delta analog-to-  
digital converter (ADC). An on-board digital filter, which  
forms part of the sigma-delta ADC, also performs critical  
system-level filtering. Due to the high level of  
oversampling, the input antialias requirements are reduced  
such that a simple single pole RC stage is sufficient to  
give adequate attenuation in the band of interest.  
Table II. P GA Settings for the Encoder Channel  
IxGS2  
IxGS1  
IxGS0  
Gain (dB)  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
6
12  
18  
20  
26  
32  
38  
S ign a l C on d ition er  
Each analog channel has an independent signal condition-  
ing block. T his allows the analog input to be configured  
by the user depending on whether differential or single-  
ended mode is used.  
P r ogr a m m a ble G a in Am p lifier  
A D C  
Each encoder section’s analog front end comprises a  
switched capacitor PGA that also forms part of the sigma-  
delta modulator. T he SC sampling frequency is DMCLK/  
8. T he PGA, whose programmable gain settings are  
shown in T able II, may be used to increase the signal  
level applied to the ADC from low output sources such as  
microphones, and can be used to avoid placing external  
Each channel has its own ADC consisting of an analog  
sigma-delta modulator and a digital antialiasing decima-  
tion filter. T he sigma-delta modulator noise-shapes the  
signal and produces 1-bit samples at a DMCLK/8 rate.  
T his bitstream, representing the analog input signal, is  
input to the antialiasing decimation filter. T he decimation  
filter reduces the sample rate and increases the resolution.  
REV. PrA  
–1 0 –  
1...78910111213...39

中文翻译

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