Datasheet > AD73560BB-40

AD73560BB-40

更新时间： 2024-02-15 01:07:15

品牌	Logo	应用领域
亚德诺 - ADI		时钟外围集成电路
页数	文件大小	规格书
39页	641K
描述
IC 0-BIT, 16.384 MHz, OTHER DSP, PBGA119, PLASTIC, BGA-119, Digital Signal Processor

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AD73560BB-40 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	BGA	包装说明：	PLASTIC, BGA-119
针数：	119	Reach Compliance Code：	not_compliant
ECCN代码：	EAR99	HTS代码：	8542.39.00.01
风险等级：	5.92	地址总线宽度：
桶式移位器：	YES	位大小：	16
边界扫描：	NO	最大时钟频率：	16.384 MHz
外部数据总线宽度：		格式：	FIXED POINT
内部总线架构：	MULTIPLE	JESD-30 代码：	R-PBGA-B119
JESD-609代码：	e0	长度：	22 mm
低功率模式：	YES	端子数量：	119
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	BGA
封装等效代码：	BGA119,7X17,50	封装形状：	RECTANGULAR
封装形式：	GRID ARRAY	峰值回流温度（摄氏度）：	NOT SPECIFIED
电源：	3.3 V	认证状态：	Not Qualified
RAM（字数）：	8192	座面最大高度：	2.27 mm
子类别：	Digital Signal Processors	最大供电电压：	3.3 V
最小供电电压：	2.7 V	标称供电电压：	3 V
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	BALL	端子节距：	1.27 mm
端子位置：	BOTTOM	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	14 mm	uPs/uCs/外围集成电路类型：	DIGITAL SIGNAL PROCESSOR, OTHER
Base Number Matches：	1

AD73560BB-40 数据手册

Preliminary Technical Data

AD73560

P IN F U NC T IO N D E SC R IP T IO N

Mnem onic

Function

VIN P1

VIN N 1

VIN P2

VIN N 2

VIN P3

VIN N 3

VIN P4

VIN N 4

VIN P5

VIN N 5

VIN P6

VIN N 6

R E F O U T

Analog Input to the Positive T erminal of Input Channel 1.

Analog Input to the Negative T erminal of Input Channel 1.

Analog Input to the Positive T erminal of Input Channel 2.

Analog Input to the Negative T erminal of Input Channel 2.

Analog Input to the Positive T erminal of Input Channel 3.

Analog Input to the Negative T erminal of Input Channel 3.

Analog Input to the Positive T erminal of Input Channel 4.

Analog Input to the Negative T erminal of Input Channel 4.

Analog Input to the Positive T erminal of Input Channel 5.

Analog Input to the Negative T erminal of Input Channel 5.

Analog Input to the Positive T erminal of Input Channel 6.

Analog Input to the Negative T erminal of Input Channel 6.

Buffered Reference Output, which has a nominal value of 1.25 V. T his pin can be overdriven by an

external reference if required.

RE F C AP

A Bypass Capacitor to AGND2 of 0.1 µF is required for the on-chip reference. T he capacitor should be

fixed to this pin.

AVD D

AG N D

D G N D

D VD D

ARE SE T

Analog Power Supply Connection.

Analog Ground/Substrate Connection.

Digital Ground/Substrate Connection.

D igital Power Supply Connection.

Active Low Reset Signal. T his input resets the entire chip, resetting the control registers and clearing the

digital circuitry.

SC LK 2

Output Serial Clock whose rate determines the serial transfer rate to/from the AFE0. It is used to

clock data or control information to and from the serial port (SPORT 2). T he frequency of SCLK is

equal to the frequency of the master clock (MCLK) divided by an integer number—this integer number

being the product of the external master clock rate divider and the serial clock rate divider.

Master Clock Input. MCLK is driven from an external clock signal.

Serial Data Output of the AD73560. Both data and control information may be output on this pin and are

clocked on the positive edge of SCLK. SDO is in three-state when no information is being transmitted and

when SE is low.

M C L K

SD O

SD OFS

SD IFS

Framing Signal Output for SDO Serial T ransfers. T he frame sync is one bit wide and it is active one SCLK

period before the first bit (MSB) of each output word. SDOFS is referenced to the positive edge of SCLK.

SDOFS is in three-state when SE is low.

Framing Signal Input for SDI Serial T ransfers. T he frame sync is one bit wide and it is valid one SCLK period

before the first bit (MSB) of each input word. SDIFS is sampled on the negative edge of SCLK and is ignored

when SE is low.

SD I

Serial Data Input of the AD73560. Both data and control information may be input on this pin and are clocked

on the negative edge of SCLK. SDI is ignored when SE is low.

SPORT Enable. Asynchronous input enable pin for the SPORT . When SE is set low by the DSP, the output

pins of the SPORT are three-stated and the input pins are ignored. SCLK is also disabled internally in order to

decrease power dissipation. When SE is brought high, the control and data registers of the SPORT are at their

original values (before SE was brought low); however, the timing counters and other internal registers are at

their reset values.

RESET

(Input) Processor Reset Input

(Input) Bus Request Input

(Output) Bus Grant Output

BG H

D M S

PM S

IOM S

BM S

C M S

(Output) Bus Grant Hung Output

(Output) Data Memory Select Output

(Output) Program Memory Select Output

(Output) Memory Select Output

(Output) Byte Memory Select Output

(Output) Combined Memory Select Output

(Output) Memory Read Enable Output

(Output) Memory Write Enable Output

IRQ2/

PF7

(Input) Edge- or Level-Sensitive Interrupt

(Input/Output) Request.¹Programmable I/O Pin

REV. PrA

–7 –

1...4 5 678 9 10...39

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