AD7278BRMJ

更新时间： 2024-01-03 03:59:39

品牌	Logo	应用领域
亚德诺 - ADI		转换器模数转换器光电二极管
页数	文件大小	规格书
20页	254K
描述
3MSPS,12-/10-/8-Bit ADCs in 6-Lead TSOT

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中文翻译

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技术参数
数据手册

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AD7278BRMJ 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	TSSOP
包装说明：	TSSOP,	针数：	8
Reach Compliance Code：	unknown	风险等级：	5.68
Is Samacsys：	N	最大模拟输入电压：	3.6 V
最小模拟输入电压：		最长转换时间：	0.291 µs
转换器类型：	ADC, SUCCESSIVE APPROXIMATION	JESD-30 代码：	S-PDSO-G8
JESD-609代码：	e3	长度：	3 mm
最大线性误差 (EL)：	0.3906%	湿度敏感等级：	1
模拟输入通道数量：	1	位数：	8
功能数量：	1	端子数量：	8
最高工作温度：	125 °C	最低工作温度：	-40 °C
输出位码：	BINARY	输出格式：	SERIAL
封装主体材料：	PLASTIC/EPOXY	封装代码：	TSSOP
封装形状：	SQUARE	封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：	260	采样速率：	3 MHz
采样并保持/跟踪并保持：	TRACK	座面最大高度：	1.1 mm
标称供电电压：	3 V	表面贴装：	YES
温度等级：	AUTOMOTIVE	端子面层：	MATTE TIN
端子形式：	GULL WING	端子节距：	0.65 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	40
宽度：	3 mm	Base Number Matches：	1

AD7278BRMJ 数据手册

PRELIMINARYTECHNICALDATA

Preliminary Technical Data

AD7276/AD7277/AD7278

SERIAL INTERFACE

elapsed, the track and hold will go back into track on the

next rising edge. If the rising edge of CS occurs before 10

SCLKs have elapsed then the part will enter Power-Down

mode. If 16 SCLKs are considered in the cycle, the

AD7278 will clock out six trailing zeros for the last six

bits and SDATA will return to three-state on the 16th

SCLK falling edge, as shown in Figure 18.

Figures 16, 17 and 18 show the detailed timing diagram

for serial interfacing to the AD7276, AD7277 and

AD7278 respectively. The serial clock provides the

conversion clock and also controls the transfer of

information from the AD7276/AD7277/AD7278 during

conversion.

The CS signal initiates the data transfer and conversion

process. The falling edge of CS puts the track and hold

into hold mode, takes the bus out of three-state and the

analog input is sampled at this point. The conversion is

also initiated at this point.

If the user considers a 14 SCLKs cycle serial interface for

the AD7276/AD7277/AD7278, CS needs to be brought

high after the 14th SCLK falling edge, the last two

trailing zeros will be ignored and SDATA will go back

into three-state. In this case, the 3MSPS throughput could

be achieved using a 45MHz clock frequency.

For the AD7276 the conversion will require 14 SCLK

cycles to complete. Once 13 SCLK falling edges have

elapsed the track and hold will go back into track on the

next SCLK rising edge as shown in Figure 16 at point B.

If the rising edge of CS occurs before 14 SCLKs have

elapsed then the conversion will be terminated and the

SDATA line will go back into three-state. If 16 SCLKs

are considered in the cycle, the last two bits will be zeros

and SDATA will return to three-state on the 16th SCLK

falling edge as shown in Figure 16.

CS going low clocks out the first leading zero to be read

in by the microcontroller or DSP. The remaining data is

then clocked out by subsequent SCLK falling edges

beginning with the 2nd leading zero. Thus the first falling

clock edge on the serial clock has the first leading zero

provided and also clocks out the second leading zero. The

final bit in the data transfer is valid on the 16th falling

edge, having being clocked out on the previous (15th)

falling edge.

For the AD7277 the conversion will require 12 SCLK

cycles to complete. Once 11 SCLK falling edges have

elapsed, the track and hold will go back into track on the

next SCLK rising edge, as shown in Figure 17 at point B.

If the rising edge of CS occurs before 12 SCLKs have

elapsed then the conversion will be terminated and the

SDATA line will go back into three-state. If 16 SCLKs

are considered in the cycle, the AD7277 will clock out

four trailing zeros for the last four bits and SDATA will

return to three-state on the 16th SCLK falling edge, as

shown in Figure 17.

In applications with a slower SCLK, it is possible to read

in data on each SCLK rising edge. In that case, the first

falling edge of SCLK will clock out the second leading

zero and it could be read in the first rising edge. However,

the first leading zero that was clocked out when CS went

low will be missed unless it was not read in the first falling

edge. The 15th falling edge of SCLK will clock out the

last bit and it could be read in the 15th rising SCLK edge.

If CS goes low just after one the SCLK falling edge has

elapsed, CS will clock out the first leading zero as before

and it may be read in the SCLK rising edge. The next

SCLK falling edge will clock out the second leading zero

and it could be read in the following rising edge.

For the AD7278 the conversion will require 10 SCLK

cycles to complete. Once 9 SCLK falling edges have

t₁

t_convert

t₂

t₆

SCLK

t₅

t₇

t₈

t_quiet

t₃

t₄

DB9

DB1

ZERO

DB11

DB10

DB0

ZERO

SDATA

THREE-

STATE

THREE-STATE

2 TRAILING

ZERO’S

2 LEADING

ZERO’S

1/ THROUGHPUT

Figure 16. AD7276 Serial Interface Timing Diagram

REV. PrF

–18–

1...15 16 171819 20

中文翻译

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与AD7278BRMJ相关器件

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AD7278BRMZ	ADI	获取价格	3 MSPS, 12-/10-/8-Bit ADCs in 6-Lead TSOT
AD7278BRMZ-REEL	ADI	获取价格	3 MSPS, 12-/10-/8-Bit ADCs in 6-Lead TSOT
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AD7278BUJZ-500RL7	ADI	获取价格	3 MSPS, 12-/10-/8-Bit ADCs in 6-Lead TSOT
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