AD7278BRMJ

更新时间： 2024-02-07 11:54:47

品牌	Logo	应用领域
亚德诺 - ADI		转换器模数转换器光电二极管
页数	文件大小	规格书
20页	254K
描述
3MSPS,12-/10-/8-Bit ADCs in 6-Lead TSOT

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中文翻译

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技术参数
数据手册

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AD7278BRMJ 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	TSSOP
包装说明：	TSSOP,	针数：	8
Reach Compliance Code：	unknown	风险等级：	5.68
Is Samacsys：	N	最大模拟输入电压：	3.6 V
最小模拟输入电压：		最长转换时间：	0.291 µs
转换器类型：	ADC, SUCCESSIVE APPROXIMATION	JESD-30 代码：	S-PDSO-G8
JESD-609代码：	e3	长度：	3 mm
最大线性误差 (EL)：	0.3906%	湿度敏感等级：	1
模拟输入通道数量：	1	位数：	8
功能数量：	1	端子数量：	8
最高工作温度：	125 °C	最低工作温度：	-40 °C
输出位码：	BINARY	输出格式：	SERIAL
封装主体材料：	PLASTIC/EPOXY	封装代码：	TSSOP
封装形状：	SQUARE	封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：	260	采样速率：	3 MHz
采样并保持/跟踪并保持：	TRACK	座面最大高度：	1.1 mm
标称供电电压：	3 V	表面贴装：	YES
温度等级：	AUTOMOTIVE	端子面层：	MATTE TIN
端子形式：	GULL WING	端子节距：	0.65 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	40
宽度：	3 mm	Base Number Matches：	1

AD7278BRMJ 数据手册

PRELIMINARYTECHNICALDATA

Preliminary Technical Data

AD7276/AD7277/AD7278

Table II provides some typical performance data with

various op-amps used as the input buffer under the same

set-up conditions.

MODES OF OPERATION

The mode of operation of the AD7276/AD7277/AD7278

is selected by controlling the logic state of the CS signal

during a conversion. There are two possible modes of

operation, Normal Mode and Power-Down Mode. The

point at which CS is pulled high after the conversion has

been initiated will determine whether the AD7276/

AD7277/AD7278 will enter Power-Down Mode or not.

Similarly, if already in Power-Down then CS can control

whether the device will return to Normal operation or

remain in Power-Down. These modes of operation are

designed to provide flexible power management options.

These options can be chosen to optimize the power dissi-

pation/throughput rate ratio for different application

requirements.

Op-amp in the

input buffer

AD7276 SNR Performance

TBD kHz Input

AD8510

AD8610

AD8038

AD8519

TBD dB

Table II. AD7276 performance for various Input Buffers

Normal Mode

This mode is intended for fastest throughput rate perfor-

mance as the user does not have to worry about any

power-up times with the AD7276/AD7277/AD7278

remaining fully powered all the time. Figure 12 shows the

general diagram of the operation of the AD7276/AD7277/

AD7278 in this mode.

When no amplifier is used to drive the analog input, the

source impedance should be limited to low values. The

maximum source impedance will depend on the amount

of total harmonic distortion (THD) that can be

tolerated. The THD will increase as the source

impedance increases and performance will degrade. TPC

7 shows a graph of the Total Harmonic Distortion

versus Analog input frequency for different source

impedances when using a supply voltage of TBD V and

sampling at a rate of 3 MSPS.

The conversion is iniated on the falling edge of CS as

described in the Serial Interface section. To ensure the

part remains fully powered up at all times CS must remain

low until at least 10 SCLK falling edges have elapsed after

the falling edge of CS. If CS is brought high any time

after the 10th SCLK falling, the part will remain powered

up but the conversion will be terminated and SDATA will

go back into three-state.

Digital Inputs

The digital inputs applied to the AD7276/AD7277/

AD7278 are not limited by the maximum ratings which

limit the analog inputs. Instead, the digitals inputs applied

can go to TBDV and are not restricted by the V_DD+ 0.3V

limit as on the analog inputs. For example, if the

AD7276/AD7277/AD7278 were operated with a V_DDof

3V then 5V logic levels could be used on the digital

inputs. However, it is important to note that the data

output on SDATA will still have 3V logic levels when

V_DDꢀ 3V. Another advantage of SCLK and CS not being

restricted by the V_DD+ 0.3V limit is the fact that power

supply sequencing issues are avoided. If CS or SCLK are

applied before V_DDthen there is no risk of latch-up as

there would be on the analog inputs if a signal greater

For the AD7276 a minimum of 14 serial clock cycles are

required to complete the conversion and access the

complete conversion result. For the AD7277 and AD7278

a minimum of 12 and 10 serial clock cycles are required

to complete the conversion and access the complete con-

version result, respectively.

CS may idle high until the next conversion or may idle

low until CS returns high sometime prior to the next

conversion (effectively idling CS low).

Once a data transfer is complete (SDATA has returned to

three-state), another conversion can be initiated after the

quiet time, t_QUIET, has elapsed by bringing CS low again.

than 0.3V was applied prior to V_DD

AD7276/77/78

SCLK

SDATA

VALID DATA

Figure 12. Normal Mode Operation

REV. PrF

–15–

1...12 13 141516 17 18...20

中文翻译

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