AD7170
ADC CIRCUIT INFORMATION
OVERVIEW
POWER-DOWN/RESET(PDRST)
PDRST
PDRST
The
When
entire ADC is powered down (including the on-chip clock), and
RDY
pin functions as a power-down pin and a reset pin.
is taken low, the AD7170 is powered down. The
The AD7170 is a low power ADC that incorporates a precision
12-bit Σ-ꢀ modulator and an on-chip digital filter intended for
measuring wide dynamic range, low frequency signals. The
device has an internal clock and one differential input. It
operates with an output data rate of 125 Hz and has a gain of 1.
A 2-wire interface simplifies data retrieval from the AD7170.
the DOUT/
are also reset. This resets the logic, the digital filter, and the analog
PDRST
pin is tristated. The circuitry and serial interface
modulator.
initiate the reset function (see Figure 4).
PDRST
must be held low for 100 ns minimum to
FILTER, DATA RATE, AND SETTLING TIME
The AD7170 uses a sinc3 filter. The output data rate is set to
125 Hz; thus, valid conversions are available every 1/125 = 8 ms.
If a reset occurs, then the user must allow the complete settling
time for the first conversion after the reset. The settling time is
equal to 24 ms. Subsequent conversions are available at 125 Hz.
When
is taken high, the AD7170 is taken out of power-
down mode. When the on-chip clock has powered up (1 ms,
typically), the modulator then begins sampling the analog input.
The DOUT/
conversion is available. A reset is automatically performed on
power-up.
RDY
pin becomes active, going high until a valid
When a step change occurs on the analog input, the AD7170
requires several conversion cycles to generate a valid conversion.
If the step change occurs synchronous to the conversion period,
then the settling time of the AD7170 must be allowed to generate
a valid conversion. If the step change occurs asynchronous to
the end of a conversion, then an extra conversion must be allowed
to generate a valid conversion. The data register is updated with
all the conversions but, for an accurate result, the user must
allow the required time.
ANALOG INPUT CHANNEL
The AD7170 has one differential analog input channel that is
connected to the modulator; that is, the input is unbuffered.
Note that this unbuffered input path provides a dynamic load
to the driving source. Therefore, resistor/capacitor combinations
on the input pins can cause dc gain errors, depending on the
output impedance of the source that is driving the ADC input.
Table 7 shows the allowable external resistance/capacitance
values such that no gain error at the 12-bit level is introduced.
Figure 12 shows the filter response of the filter. The only external
filtering required on the analog inputs is a simple R-C filter to
provide rejection at multiples of the master clock. A 1 KΩ
resistor in series with each analog input, a 0.01 μF capacitor
from each input to GND, and a 0.1 μF capacitor from AIN(+) to
AIN(−) are recommended.
Table 7. External R-C Combination for No Gain Error
C (pF)
R (Ω)
50
9 k
100
6 k
500
1.5 k
900
200
0
1000
5000
–10
–20
–30
The absolute input voltage range is restricted to a range between
GND − 30 mV and VDD + 30 mV. Care must be taken in setting up
the common-mode voltage to avoid exceeding these limits. Other-
wise, there is degradation in linearity and noise performance.
–40
–50
–60
BIPOLAR CONFIGURATION
–70
–80
The AD7170 accepts a bipolar input range. A bipolar input
range does not imply that the part can tolerate negative voltages
with respect to system GND. Signals on the AIN(+) input are
referenced to the voltage on the AIN(−) input. For example, if
AIN(−) is 2.5 V, the analog input range on the AIN(+) input is
0 V to 5 V when a 2.5 V reference is used.
–90
–100
0
125
250
375
500
625
750
INPUT SIGNAL FREQUENCY (Hz)
Figure 12. Filter Response
GAIN
The AD7170 has a gain of 1. The acceptable analog input range
is +VREF. Therefore, with VREF = 5 V, the input range is +5 V.
Rev. 0 | Page 10 of 16
5秒后页面跳转
STM32H743技术深度剖析与应用案例探索
LM321中文资料解析：引脚功能介绍、技术特点、技术特性分析
74HC14芯片资料介绍：性能特性分析、引脚介绍
LM1875芯片手册：功放参数分析、引脚说明、电路设计要点
微信公众号
抖音公众号
浙公网安备 33010502006866号 浙ICP备10014259号-119
营业执照ICP证
数据手册
如果您发现信息不准确，
