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AD7176-2BRUZ PDF预览

AD7176-2BRUZ

更新时间: 2024-02-14 12:25:46
品牌 Logo 应用领域
亚德诺 - ADI 转换器
页数 文件大小 规格书
68页 959K
描述
The AD7176-2 is a fast settling, highly accurate, high resolution, multiplexed Σ-Δ analog-to-digital converter (ADC) for low band-width input signals.

AD7176-2BRUZ 技术参数

Source Url Status Check Date:2013-05-01 14:56:16.775是否无铅: 含铅
是否Rohs认证: 符合生命周期:Active
包装说明:TSSOP, TSSOP24,.25针数:24
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.43
最大模拟输入电压:2.5 V最小模拟输入电压:-2.5 V
转换器类型:ADC, DELTA-SIGMAJESD-30 代码:R-PDSO-G24
JESD-609代码:e3长度:7.8 mm
最大线性误差 (EL):714%湿度敏感等级:3
模拟输入通道数量:4位数:24
功能数量:1端子数量:24
最高工作温度:105 °C最低工作温度:-40 °C
输出位码:OFFSET BINARY输出格式:SERIAL
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP24,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):260
电源:2.5/5,5 V认证状态:Not Qualified
采样速率:0.25 MHz座面最大高度:1.2 mm
子类别:Analog to Digital Converters标称供电电压:5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:4.4 mmBase Number Matches:1

AD7176-2BRUZ 数据手册

 浏览型号AD7176-2BRUZ的Datasheet PDF文件第2页浏览型号AD7176-2BRUZ的Datasheet PDF文件第3页浏览型号AD7176-2BRUZ的Datasheet PDF文件第4页浏览型号AD7176-2BRUZ的Datasheet PDF文件第5页浏览型号AD7176-2BRUZ的Datasheet PDF文件第6页浏览型号AD7176-2BRUZ的Datasheet PDF文件第7页 
24-Bit, 250 kSPS Sigma-Delta ADC  
with 20 µs Settling  
Data Sheet  
AD7176-2  
FEATURES  
GENERAL DESCRIPTION  
Fast and flexible output rate—5 SPS to 250 kSPS  
Fast settling time—20 µs  
Channel scan data rate of 50 kSPS/channel  
Performance specifications  
17 noise free bits at 250 kSPS  
20 noise free bits at 2.5 kSPS  
The AD7176-2 is a fast settling, highly accurate, high resolution,  
multiplexed Σ-Δ analog-to-digital converter (ADC) for low band-  
width input signals. Its inputs can be configured as two fully  
differential or four pseudo differential inputs via the integrated  
crosspoint multiplexer. An integrated precision, 2.5 V, low drift  
(2 ppm/°C), band gap internal reference (with an output  
reference buffer) adds functionality and reduces the external  
component count.  
22 noise free bits at 5 SPS  
INL 2.5 ppm of FSR  
85 dB rejection of 50 Hz and 60 Hz with 50 ms settling  
User-configurable input channels  
2 fully differential or 4 pseudo differential  
Crosspoint multiplexer  
On-chip 2.5 V reference (drift 2 ppm/°C)  
Internal oscillator, external crystal, or external clock  
Power supply  
Single supply: 5 V AVDD1, 2 V to 5 V AVDD2 and IOVDD  
Optional split supply: AVDD1 and AVSS 2.5 V  
Current: 7.8 mA  
Temperature range: −40°C to +105°C  
3- or 4-wire serial digital interface (Schmitt trigger on SCLK)  
CRC error checking  
The maximum channel scan data rate is 50 kSPS (with a settling  
time of 20 µs), resulting in fully settled data of 17 noise free bits.  
User-selectable output data rates range from 5 SPS to 250 kSPS.  
The resolution increases at lower speeds.  
The AD7176-2 offers three key digital filters. The fast settling filter  
maximizes the channel scan rate. The Sinc3 filter maximizes the  
resolution for single-channel, low speed applications. For 50 Hz  
and 60 Hz environments, the AD7176-2 specific filter minimizes  
the settling times or maximizes the rejection of the line frequency.  
These enhanced filters enable simultaneous 50 Hz and 60 Hz rejec-  
tion with a 27 SPS output data rate (with a settling time of 36 ms).  
System offset and gain errors can be corrected on a per channel  
basis. This per channel configurability extends to the type of filter  
and output data rate used for each channel. All switching of the  
crosspoint multiplexer is controlled by the ADC and can be con-  
figured to automatically control an external multiplexer via the  
GPIO pins.  
SPI, QSPI, MICROWIRE, and DSP compatible  
APPLICATIONS  
Process control: PLC/DCS modules  
Temperature and pressure measurement  
Medical and scientific multichannel instrumentation  
Chromatography  
The specified operating temperature range is −40°C to +105°C.  
The AD7176-2 is housed in a 24-lead TSSOP package.  
FUNCTIONAL BLOCK DIAGRAM  
AVDD1 AVDD2 REGCAPA REF– REF+ REFOUT  
IOVDD REGCAPD  
BUFFERED  
PRECISION  
REFERENCE  
1.8V  
LDO  
1.8V  
LDO  
INT  
REF  
AIN0  
AIN1  
CS  
SCLK  
SERIAL  
DIGITAL  
FILTER  
INTERFACE  
AND CONTROL  
Σ-Δ ADC  
DIN  
AIN2  
DOUT/RDY  
SYNC/ERROR  
AIN3  
XTAL AND INTERNAL  
CLOCK OSCILLATOR  
CIRCUITRY  
I/O  
CONTROL  
AIN4  
AD7176-2  
CROSSPOINT  
MULTIPLEXER  
AVSS  
GPIO0 GPIO1  
XTAL1 CLKIO/XTAL2  
DGND  
Figure 1.  
Rev. 0  
Document Feedback  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
rightsof third parties that may result fromits use. Specifications subject to change without notice. No  
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.  
Trademarks andregisteredtrademarks are the property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
Technical Support  
©2012 Analog Devices, Inc. All rights reserved.  
www.analog.com  
 
 
 
 

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