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AD7190_08

更新时间: 2022-12-26 19:16:08
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
40页 744K
描述
4.8 kHz Ultralow Noise 24-Bit Sigma-Delta ADC with PGA

AD7190_08 数据手册

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4.8 kHz Ultralow Noise 24-Bit  
Sigma-Delta ADC with PGA  
AD7190  
Chromatography  
FEATURES  
PLC/DCS analog input modules  
Data acquisition  
Medical and scientific instrumentation  
RMS noise: 8.5 nV @ 4.7 Hz (gain = 128)  
16 noise free bits @ 2.4 kHz (gain = 128)  
Up to 22.5 noise free bits (gain = 1)  
Offset drift: 5 nV/°C  
GENERAL DESCRIPTION  
Gain drift: 1 ppm/°C  
The AD7190 is a low noise, complete analog front end for high  
precision measurement applications. It contains a low noise,  
24-bit sigma-delta (∑-Δ) analog to digital converter (ADC).  
The on-chip low noise gain stage means that signals of small  
amplitude can be interfaced directly to the ADC.  
Specified drift over time  
2 differential/4 pseudo differential input channels  
Automatic channel sequencer  
Programmable gain (1 to 128)  
Output data rate: 4.7 Hz to 4.8 kHz  
Internal or external clock  
Simultaneous 50 Hz/60 Hz rejection  
4 general-purpose digital outputs  
Power supply  
AVDD: 4.75 V to 5.25 V  
DVDD: 2.7 V to 5.25 V  
Current: 6 mA  
Temperature range: –40°C to +105°C  
Interface  
The device can be configured to have two differential inputs or  
four pseudo differential inputs. The on-chip channel sequencer  
allows several channels to be enabled, and the AD7190  
sequentially converts on each enabled channel. This simplifies  
communication with the part. The on-chip 4.92 MHz clock can  
be used as the clock source to the ADC or, alternatively, an  
external clock or crystal can be used. The output data rate from  
the part can be varied from 4.7 Hz to 4.8 kHz.  
The device has two digital filter options. The choice of filter  
affects the rms noise/noise-free resolution at the programmed  
output data rate, the settling time, and the 50 Hz/60 Hz  
rejection. For applications that require all conversions to be  
settled, the AD7190 includes a zero latency feature.  
3-wire serial  
SPI, QSPI™, MICROWIRE™, and DSP compatible  
Schmitt trigger on SCLK  
APPLICATIONS  
The part operates with 5 V analog power supply and a digital  
power supply from 2.7 V to 5.25 V. It consumes a current of  
6 mA. It is housed in a 24-lead TSSOP package.  
Weigh scales  
Strain gauge transducers  
Pressure measurement  
Temperature measurement  
FUNCTIONAL BLOCK DIAGRAM  
AGND AV  
DV  
DGND REFIN1(+) REFIN1(–)  
DD  
DD  
REFERENCE  
DETECT  
AD7190  
AIN1  
AIN2  
AIN3  
DOUT/RDY  
SERIAL  
INTERFACE  
AND  
CONTROL  
LOGIC  
AIN4  
MUX  
DIN  
Σ-Δ  
ADC  
AINCOM  
PGA  
SCLK  
CS  
SYNC  
TEMP  
SENSOR  
P3  
P2  
BPDSW  
CLOCK  
CIRCUITRY  
AGND  
MCLK1 MCLK2 P0/REFIN2(–) P1/REFIN2(+)  
Figure 1.  
Rev. 0  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
rights of third parties that may result from its use. Specifications subject to change without notice. No  
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.  
Trademarks and registeredtrademarks arethe property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
Fax: 781.461.3113  
www.analog.com  
©2008 Analog Devices, Inc. All rights reserved.  
 

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