5秒后页面跳转
AD7190_08 PDF预览

AD7190_08

更新时间: 2022-12-26 19:16:08
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
40页 744K
描述
4.8 kHz Ultralow Noise 24-Bit Sigma-Delta ADC with PGA

AD7190_08 数据手册

 浏览型号AD7190_08的Datasheet PDF文件第1页浏览型号AD7190_08的Datasheet PDF文件第2页浏览型号AD7190_08的Datasheet PDF文件第3页浏览型号AD7190_08的Datasheet PDF文件第5页浏览型号AD7190_08的Datasheet PDF文件第6页浏览型号AD7190_08的Datasheet PDF文件第7页 
AD7190  
Parameter  
AD7190B  
Unit  
Test Conditions/Comments1  
External Clock  
@ ±0 Hz, 60 Hz  
120  
82  
dB min  
dB min  
10 Hz output data rate, ±0 ± 1 Hz, 60 ± 1 Hz.  
±0 Hz output data rate, REJ60± = 1,  
±0 ± 1 Hz, 60 ± 1 Hz.  
@ ±0 Hz  
@ 60 Hz  
120  
120  
dB min  
dB min  
±0 Hz output data rate, ±0 ± 1 Hz.  
60 Hz output data rate, 60 ± 1 Hz.  
Sinc3 Filter  
Internal Clock  
@ ±0 Hz, 60 Hz  
7±  
60  
dB min  
dB min  
10 Hz output data rate, ±0 ± 1 Hz, 60 ± 1 Hz.  
±0 Hz output data rate, REJ60± = 1,  
±0 ± 1 Hz, 60 ± 1 Hz.  
@ ±0 Hz  
@ 60 Hz  
72  
72  
dB min  
dB min  
±0 Hz output data rate, ±0 ± 1 Hz.  
60 Hz output data rate, 60 ± 1 Hz.  
External Clock  
@ ±0 Hz, 60 Hz  
100  
67  
dB min  
dB min  
10 Hz output data rate, ±0 ± 1 Hz, 60 ± 1 Hz.  
±0 Hz output data rate, REJ60± = 1,  
±0 ± 1 Hz, 60 ± 1 Hz.  
@ ±0 Hz  
@ 60 Hz  
100  
100  
dB min  
dB min  
±0 Hz output data rate, ±0 ± 1 Hz.  
60 Hz output data rate, 60 ± 1 Hz.  
ANALOG INPUTS  
Differential Input Voltage Ranges  
±VREF5gain  
V nom  
VREF = REFINx(+) − REFINx(−),  
gain = 1 to 128.  
±(AVDD – 1.2± V)5gain  
V min5max  
gain > 1.  
Absolute AIN Voltage Limits2  
Unbuffered Mode  
GND − ±0 mV  
AVDD + ±0 mV  
GND + 2±0 mV  
AVDD − 2±0 mV  
V min  
V max  
V min  
V max  
Buffered Mode  
Analog Input Current  
Buffered Mode  
Input Current2  
±2  
±3  
±±  
nA max  
nA max  
pA5°C typ  
Gain = 1.  
Gain > 1.  
Input Current Drift  
Unbuffered Mode  
Input Current  
±±  
μA5V typ  
Gain = 1, input current varies with input  
voltage.  
±1  
μA5V typ  
Gain > 1.  
Input Current Drift  
±0.0±  
±1.6  
nA5V5°C typ  
nA5V5°C typ  
External clock.  
Internal clock.  
REFERENCE INPUT  
REFIN Voltage  
Reference Voltage Range2  
AVDD  
1
AVDD  
V nom  
V min  
V max  
REFIN = REFINx(+) − REFINx(−).  
The differential input must be limited to  
± (AVDD – 1.2± V)5gain when gain > 1.  
Absolute REFIN Voltage Limits2  
Average Reference Input Current  
Average Reference Input Current  
Drift  
GND – ±0 mV  
AVDD + ±0 mV  
7
V min  
V max  
μA5V typ  
nA5V5°C typ  
±0.03  
External clock.  
Internal clock.  
1.3  
nA5V5°C typ  
Rev. 0 | Page 4 of 40  

与AD7190_08相关器件

型号 品牌 描述 获取价格 数据表
AD7190BRUZ ADI 4.8 kHz Ultralow Noise 24-Bit Sigma-Delta ADC with PGA

获取价格

AD7190BRUZ-REEL ADI 4.8 kHz Ultralow Noise 24-Bit Sigma-Delta ADC with PGA

获取价格

AD7190WBRUZ ADI 4.8 kHz Ultralow Noise 24-Bit Sigma-Delta ADC with PGA

获取价格

AD7190WBRUZ-RL ADI 1-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO24, ROHS COMPLIANT, TSSOP-24

获取价格

AD7191 ADI Pin-Programmable, Ultralow Noise, 24-Bit, Sigma-Delta ADC for Bridge Sensors

获取价格

AD7191BRUZ ADI Pin-Programmable, Ultralow Noise, 24-Bit, Sigma-Delta ADC for Bridge Sensors

获取价格