Quad, 16-/12-Bit nanoDAC+
with I2C Interface
Data Sheet
AD5696/AD5694
FEATURES
FUNCTIONAL BLOCK DIAGRAM
V
GND
V
REF
DD
High relative accuracy (INL): 2 LSB maximum at 16 bits
Tiny package: 3 mm × 3 mm, 16-lead LFCSP
Total unadjusted error (TUE): 0.1% of FSR maximum
AD5696/AD5694
V
LOGIC
SCL
STRING
DAC A
INPUT
REGISTER
DAC
REGISTER
V
V
V
V
A
B
C
D
OUT
OUT
OUT
OUT
Offset error: 1.5 mV maximum
Gain error: 0.1% of FSR maximum
High drive capability: 20 mA, 0.5 V from supply rails
User-selectable gain of 1 or 2 (GAIN pin)
Reset to zero scale or midscale (RSTSEL pin)
1.8 V logic compatibility
BUFFER
BUFFER
BUFFER
BUFFER
STRING
DAC B
INPUT
DAC
REGISTER
REGISTER
SDA
A1
STRING
DAC C
INPUT
REGISTER
DAC
REGISTER
A0
400 kHz I2C-compatible serial interface
4 I2C addresses available
STRING
DAC D
INPUT
REGISTER
DAC
REGISTER
Low glitch: 0.5 nV-sec
Robust 3.5 kV HBM and 1.5 kV FICDM ESD rating
Low power: 1.8 mW at 3 V
POWER-ON
RESET
GAIN =
×1/×2
POWER-
DOWN
LOGIC
LDAC RESET
RSTSEL
GAIN
2.7 V to 5.5 V power supply
−40°C to +105°C temperature range
Figure 1.
APPLICATIONS
Digital gain and offset adjustment
Programmable attenuators
Process control (PLC I/O cards)
Industrial automation
Data acquisition systems
Table 1. Quad nanoDAC+ Devices
GENERAL DESCRIPTION
Interface
Reference 16-Bit
14-Bit
12-Bit
The AD5696 and AD5694, members of the nanoDAC+™ family,
are low power, quad, 16-/12-bit buffered voltage output DACs.
The devices include a gain select pin giving a full-scale output
of 2.5 V (gain = 1) or 5 V (gain = 2). The devices operate from
a single 2.7 V to 5.5 V supply, are guaranteed monotonic by
design, and exhibit less than 0.1% FSR gain error and 1.5 mV
offset error performance. The devices are available in a 3 mm ×
3 mm LFCSP package and in a TSSOP package.
SPI
Internal
External
Internal
External
AD5686R
AD5685R
AD5684R
AD5684
AD5694R
AD5694
AD5686
AD5696R
AD5696
I2C
AD5695R
PRODUCT HIGHLIGHTS
1. High Relative Accuracy (INL).
AD5696 (16-bit): 2 LSB maximum
AD5694 (12-bit): 1 LSB maximum
2. Excellent DC Performance.
Total unadjusted error: 0.1% of FSR maximum
Offset error: 1.5 mV maximum
Gain error: 0.1% of FSR maximum
3. Two Package Options.
The AD5696/AD5694 incorporate a power-on reset circuit and a
RSTSEL pin; the RSTSEL pin ensures that the DAC outputs power
up to zero scale or midscale and remain at that level until a valid
write takes place. The parts contain a per-channel power-down
feature that reduces the current consumption of the device in
power-down mode to 4 µA at 3 V.
The AD5696/AD5694 use a versatile 2-wire serial interface that
operates at clock rates up to 400 kHz and include a VLOGIC pin
intended for 1.8 V/3 V/5 V logic.
3 mm × 3 mm, 16-lead LFCSP
16-lead TSSOP
Rev. A
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