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AD5371BBCZ

更新时间： 2024-09-17 04:30:39
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亚德诺 - ADI /
页数 文件大小 规格书
25页 295K
描述
40-Channel, 14-Bit Serial Input, Voltage-Output DAC

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AD5371BBCZ 数据手册

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40-Channel, 14-Bit  
Serial Input, Voltage-Output DAC  
Preliminary Technical Data  
AD5371  
Power-on reset  
Digital reset (RESET)  
FEATURES  
40-channel DAC in 80 Lead LQFP and 100 Ball CSPBGA  
Clear function to user-defined SIGGND (CLR pin)  
Simultaneous update of DAC outputs (LDAC pin)  
Guaranteed monotonic to 14 bits  
Maximum output voltage span of 4 × VREF (20 V)  
Nominal output voltage range of -4 V to +8 V  
Multiple, Independent output spans available  
System calibration function allowing user-programmable  
offset and gain  
Channel grouping and addressing features  
Thermal Monitor Function  
DSP/microcontroller-compatible serial interface  
LVDS serial interface  
APPLICATIONS  
Level setting in automatic test equipment (ATE)  
Variable optical attenuators (VOA)  
Optical switches  
Industrial control systems  
Instrumentation  
2.5 V to 5.5 V JEDEC-compliant digital levels  
FUNCTIONAL BLOCK DIAGRAM  
DV  
V
V
SS  
AGND DNGD  
CC  
DD  
LDAC  
VREF0  
GROUP 0  
BUFFER  
14  
CONTROL  
REGISTER  
14  
14  
14  
14  
OFFSET  
DAC 0  
OFS0  
REGISTER  
8
8
A/B SELECT  
REGISTER  
TO  
MUX 2's  
BUFFER  
OUTPUT BUFFER  
AND POWER  
DOWN CONTROL  
14  
VOUT0  
VOUT1  
VOUT2  
VOUT3  
VOUT4  
VOUT5  
VOUT6  
VOUT7  
14  
14  
14  
X1A REGISTER  
X2A REGISTER  
DAC 0  
REGISTER  
MUX  
2
MUX  
1
DAC 0  
14  
14  
X2B REGISTER  
X1B REGISTER  
M REGISTER  
C REGISTER  
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
14  
14  
SPI/LVDS  
SYNC  
SDI  
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
OUTPUT BUFFER  
AND POWER  
·
SCLK  
SYNC  
SDI  
14  
14  
14  
14  
14  
14  
X1A REGISTER  
X2A REGISTER  
SERIAL  
INTERFACE  
DAC 7  
MUX  
2
MUX  
1
DAC 7  
DOWN CONTROL  
14  
14  
SIGGND0  
REGISTER  
X2B REGISTER  
X1B REGISTER  
M REGISTER  
C REGISTER  
14  
SCLK  
SDO  
14  
VREF1  
GROUP 1  
14  
14  
14  
14  
OFFSET  
DAC 1  
OFS1  
REGISTER  
BUSY  
8
8
TO  
MUX 2's  
A/B SELECT  
REGISTER  
BUFFER  
RESET  
CLR  
OUTPUT BUFFER  
AND POWER  
DOWN CONTROL  
14  
VOUT8  
14  
14  
14  
X1A REGISTER  
X2A REGISTER  
DAC 0  
REGISTER  
MUX  
2
MUX  
1
DAC 0  
VOUT9  
14  
14  
X2B REGISTER  
X1B REGISTER  
M REGISTER  
C REGISTER  
VOUT10  
VOUT11  
VOUT12  
VOUT13  
VOUT14  
VOUT15  
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
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·
·
·
·
·
·
STATE  
MACHINE  
14  
14  
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
14  
OUTPUT BUFFER  
AND POWER  
·
14  
14  
14  
14  
POWER-ON  
RESET  
14  
14  
X1A REGISTER  
X2A REGISTER  
DAC 7  
MUX  
2
MUX  
1
DAC 7  
DOWN CONTROL  
14  
14  
SIGGND1  
REGISTER  
X2B REGISTER  
X1B REGISTER  
M REGISTER  
C REGISTER  
14  
14  
AD5371  
VREF2 SUPPLIES  
GROUPS 2 TO 4  
VREF2  
GROUPS 2 TO 4  
SAME AS GROUP 1  
VOUT16  
TO  
VOUT39  
5371-0001  
SIGGND3  
SIGGND4  
SIGGND2  
Figure 1.  
AD5371—Protected by U.S. Patent No. 5,969,657; other patents pending  
Rev. PrF  
Information furnished by Analog Devices is believed to be accurate and reliable.  
However, no responsibility is assumed by Analog Devices for its use, nor for any  
infringements of patents or other rights of third parties that may result from its use.  
Specifications subject to change without notice. No license is granted by implication  
or otherwise under any patent or patent rights of Analog Devices. Trademarks and  
registered trademarks are the property of their respective companies.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
Fax: 781.326.8703  
www.analog.com  
© 2006 Analog Devices, Inc. All rights reserved.  
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