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AD5323BRUZ-REEL7 PDF预览

AD5323BRUZ-REEL7

更新时间： 2024-01-01 02:09:21
品牌 Logo 应用领域
亚德诺 - ADI 光电二极管转换器
页数 文件大小 规格书
28页 488K
描述
2.5 V to 5.5 V, 230 µA, Dual Rail-to-Rail Voltage Output 12-Bit DAC

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AD5323BRUZ-REEL7 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：TSSOP
包装说明：TSSOP,针数：16
Reach Compliance Code：unknown风险等级：5.73
最大模拟输出电压：5.499 V最小模拟输出电压：0.001 V
转换器类型：D/A CONVERTER输入位码：BINARY
输入格式：SERIALJESD-30 代码：R-PDSO-G16
JESD-609代码：e3长度：5 mm
最大线性误差 (EL)：0.1953%湿度敏感等级：1
位数：12功能数量：1
端子数量：16最高工作温度：105 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度（摄氏度）：260
认证状态：COMMERCIAL座面最大高度：1.2 mm
标称安定时间 (tstl)：8 µs标称供电电压：3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：MATTE TIN
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL处于峰值回流温度下的最长时间：40
宽度：4.4 mmBase Number Matches：1

AD5323BRUZ-REEL7 数据手册

 浏览型号AD5323BRUZ-REEL7的Datasheet PDF文件第20页浏览型号AD5323BRUZ-REEL7的Datasheet PDF文件第21页浏览型号AD5323BRUZ-REEL7的Datasheet PDF文件第22页浏览型号AD5323BRUZ-REEL7的Datasheet PDF文件第24页浏览型号AD5323BRUZ-REEL7的Datasheet PDF文件第25页浏览型号AD5323BRUZ-REEL7的Datasheet PDF文件第26页 
AD5303/AD5313/AD5323  
A continuous SCLK source may be used if it can be arranged  
COARSE AND FINE ADJUSTMENT USING THE  
AD5303/AD5313/AD5323  
SYNC  
that  
is held low for the correct number of clock cycles.  
Alternatively, a burst clock containing the exact number of  
The DACs in the AD5303/AD5313/AD5323 can be paired  
together to form a coarse and fine adjustment function, as  
shown in Figure 45. DAC A provides the coarse adjustment  
while DAC B provides the fine adjustment. Varying the ratio  
of R1 and R2 changes the relative effect of the coarse and fine  
adjustments. With the resistor values and external reference  
shown, the output amplifier has unity gain for the DAC A  
output, so the output range is 0 V to 2.5 V − 1 LSB. For  
DAC B, the amplifier has a gain of 7.6 × 10–3, giving DAC B  
a range equal to 19 mV.  
SYNC  
clock cycles may be used and  
time later.  
may be taken high some  
When the transfer to all input registers is complete, a common  
LDAC  
signal updates all DAC registers and all analog outputs  
are updated simultaneously.  
AD5303/  
AD5313/  
AD53231  
(DAC 1)  
68HC111  
MOSI  
SCK  
DIN  
SCLK  
The circuit is shown with a 2.5 V reference, but reference  
voltages up to VDD may be used. The op amps indicated allow  
a rail-to-rail output swing.  
SYNC  
LDAC  
PC7  
PC6  
MISO  
SDO  
DIN  
V
= 5V  
DD  
R3  
R4  
AD5303/  
AD5313/  
AD53231  
(DAC 2)  
51.2kΩ  
900Ω  
+5V  
0.1µF  
1µF  
10µF  
V
IN  
SCLK  
SYNC  
LDAC  
EXT 2.5V  
REF  
V
DD  
V
OUT  
R1  
V
OUT  
V
A
V
A
OUT  
REF  
AD820/  
OP295  
390Ω  
GND  
SDO  
AD5303/AD5313/  
AD5323  
AD780/REF192  
WITH V = 5V  
DIN  
DD  
R2  
AD5303/  
AD5313/  
AD53231  
(DAC N)  
V
B
V
B
OUT  
REF  
51.2kΩ  
GND  
SCLK  
SYNC  
LDAC  
Figure 45. Coarse and Fine Adjustment  
SDO  
DAISY-CHAIN MODE  
1
ADDITIONAL PINS OMITTED FOR CLARITY.  
This mode is used for updating serially connected or standalone  
SYNC  
Figure 46. Daisy-Chain Mode  
devices on the rising edge of  
. For systems that contain  
several DACs, or where the user wishes to read back the DAC  
contents for diagnostic purposes, the SDO pin may be used to  
daisy-chain several devices together and provide serial readback.  
By connecting the daisy-chain enable (DCEN) pin high, the  
daisy-chain mode is enabled. It is tied low in standalone mode.  
In daisy-chain mode, the internal gating on SCLK is disabled.  
The SCLK is continuously applied to the input shift register  
SYNC  
when  
is low. If more than 16 clock pulses are applied,  
the data ripples out of the shift register and appears on the SDO  
line. This data is clocked out after the falling edge of SCLK and  
is valid on the subsequent rising and falling edges. By connect-  
ing this line to the DIN input on the next DAC in the chain, a  
multiDAC interface is constructed. Sixteen clock pulses are  
required for each DAC in the system. Therefore, the total  
number of clock cycles must equal 16N, where N is the total  
number of devices in the chain. When the serial transfer to all  
SYNC  
devices is complete,  
should be taken high. This prevents  
any further data from being clocked into the input shift register.  
Rev. B | Page 23 of 28  
 
 
 
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