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ACTS74MS

更新时间： 2024-09-18 14:58:19
品牌 Logo 应用领域
瑞萨 - RENESAS /
页数 文件大小 规格书
3页 120K
描述
CMOS Dual D Type Flip Flop with Set and Reset, Advanced Logic

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ACTS74MS 数据手册

 浏览型号ACTS74MS的Datasheet PDF文件第2页浏览型号ACTS74MS的Datasheet PDF文件第3页 
TM  
ACTS74MS  
Radiation Hardened Dual D  
Flip Flop with Set and Reset  
January 1996  
Features  
Pinouts  
14 PIN CERAMIC DUAL-IN-LINE  
MIL-STD-1835 DESIGNATOR CDIP2-T14,  
LEAD FINISH C  
• Devices QML Qualified in Accordance with MIL-PRFF-38535  
• Detailed Electrical and Screening Requirements are Contained in  
SMD# 5962-96713 and Intersil’s QM Plan  
itle  
CTS  
MS)  
b-  
TOP VIEW  
• 1.25 Micron Radiation Hardened SOS CMOS  
R1  
D1  
1
2
3
4
5
6
7
14 VCC  
13 R2  
12 D2  
11 CP2  
10 S2  
• Total Dose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >300K RAD (Si)  
-10  
t
• Single Event Upset (SEU) Immunity: <1 x 10  
(Typ)  
Errors/Bit/Day  
CP1  
S1  
adia-  
n
rd-  
ed  
al D  
p
p
th  
tand  
set)  
2
• SEU LET Threshold . . . . . . . . . . . . . . . . . . . . . . . >100 MEV-cm /mg  
Q1  
11  
• Dose Rate Upset . . . . . . . . . . . . . . . . >10 RAD (Si)/s, 20ns Pulse  
Q1  
9
8
Q2  
Q2  
12  
• Dose Rate Survivability. . . . . . . . . . . >10 RAD (Si)/s, 20ns Pulse  
GND  
• Latch-Up Free Under Any Conditions  
o
o
• Military Temperature Range . . . . . . . . . . . . . . . . . . -55 C to +125 C  
• Significant Power Reduction Compared to ALSTTL Logic  
• DC Operating Voltage Range . . . . . . . . . . . . . . . . . . . . 4.5V to 5.5V  
14 PIN CERAMIC FLATPACK  
MIL-STD-1835 DESIGNATOR CDFP3-F14,  
LEAD FINISH C  
• Input Logic Levels  
- VIL = 0.8V Max  
TOP VIEW  
1
2
3
4
5
6
7
14  
13  
VCC  
R2  
thor  
R1  
D1  
- VIH = VCC/2 Min  
• Input Current ≤ 1µA at VOL, VOH  
D2  
12  
11  
10  
CP1  
S1  
ey-  
rds  
ter-  
CP2  
S2  
• Fast Propagation Delay. . . . . . . . . . . . . . . . 20ns (Max), 13ns (Typ)  
Q1  
Q2  
Q1  
9
8
Description  
Q2  
GND  
The Intersil ACTS74MS is a Radiation Hardened Dual D Flip Flop with  
Set(s) and Reset (R). The logic level at data input is transferred to the  
output during the positive transition of the clock. The Set and Reset are  
independent from the clock and accomplished by a low level on the  
appropriate input.  
mi-  
n-  
ctor,  
dia-  
n
rd-  
ed,  
,
The ACTS74MS utilizes advanced CMOS/SOS technology to achieve  
high-speed operation. This device is a member of a radiation hardened,  
high-speed, CMOS/SOS Logic Family.  
The ACTS74MS is supplied in a 14 lead Ceramic Flatpack (K suffix) or a  
14 Lead Ceramic Dual-In-Line Package (D suffix).  
d
Ordering Information  
rd,  
L,  
tel-  
,
D,  
ass  
PART NUMBER  
5962F9671301VCC  
5962F9671301VXC  
ACTS74D/Sample  
ACTS74K/Sample  
ACTS74HMSR  
TEMPERATURE RANGE  
-55oC to +125oC  
-55oC to +125oC  
25oC  
SCREENING LEVEL  
PACKAGE  
MIL-PRF-38535 Class V  
14 Lead SBDIP  
MIL-PRF-38535 Class V  
14 Lead Ceramic Flatpack  
14 Lead SBDIP  
Sample  
Sample  
Die  
25oC  
14 Lead Ceramic Flatpack  
Die  
25oC  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Americas Inc.  
Spec Number 518787  
File Number 3382.1  
Copyright © Intersil Americas Inc. 2001, All Rights Reserved  
1
123

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ACTS86K INTERSIL

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ACTS86K/SAMPLE-02 RENESAS

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