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ACTS86DMSR

更新时间： 2024-09-16 22:49:55
品牌 Logo 应用领域
英特矽尔 - INTERSIL 触发器逻辑集成电路石英晶振栅
页数 文件大小 规格书
8页 89K
描述
Radiation Hardened Quad 2-Input Exclusive OR Gate

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中文翻译

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ACTS86DMSR 数据手册

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ACTS86MS  
Radiation Hardened  
Quad 2-Input Exclusive OR Gate  
April 1995  
Features  
Pinouts  
14 LEAD CERAMIC DUAL-IN-LINE  
MIL-STD-1835 DESIGNATOR, CDIP2-T14, LEAD FINISH C  
TOP VIEW  
• 1.25 Micron Radiation Hardened SOS CMOS  
• Total Dose 300K RAD (Si)  
• Single Event Upset (SEU) Immunity  
<1 x 10-10 Errors/Bit-Day (Typ)  
A1  
B1  
1
2
3
4
5
6
7
14 VCC  
13 B4  
12 A4  
11 Y4  
10 B3  
• SEU LET Threshold >80 MEV-cm2/mg  
Y1  
• Dose Rate Upset >1011 RAD (Si)/s, 20ns Pulse  
A2  
• Latch-Up Free Under Any Conditions  
B2  
• Military Temperature Range: -55oC to +125oC  
• Significant Power Reduction Compared to ALSTTL Logic  
• DC Operating Voltage Range: 4.5V to 5.5V  
Y2  
9
8
A3  
Y3  
GND  
• Input Logic Levels  
- VIL = 0.8V Max  
14 LEAD CERAMIC FLATPACK  
MIL-STD-1835 DESIGNATOR, CDFP3-F14, LEAD FINISH C  
TOP VIEW  
- VIH = VCC/2V Min  
• Input Current ≤1µA at VOL, VOH  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
VCC  
B4  
A4  
Y4  
A1  
B1  
Description  
Y1  
The Intersil ACTS86MS is a radiation hardened quad 2-input  
exclusive OR gate. A high logic level on any one input exclu-  
sively will change the output to a high logic state.  
A2  
B2  
B3  
A3  
Y3  
Y2  
The ACTS86MS utilizes advanced CMOS/SOS technology to  
achieve high-speed operation. This device is a member of the  
radiation hardened, high-speed, CMOS/SOS Logic Family.  
GND  
8
Ordering Information  
PART NUMBER  
ACTS86DMSR  
TEMPERATURE RANGE  
SCREENING LEVEL  
Intersil Class S Equivalent  
Intersil Class S Equivalent  
Sample  
PACKAGE  
o
o
-55 C to +125 C  
14 Lead SBDIP  
o
o
ACTS86KMSR  
-55 C to +125 C  
14 Lead Ceramic Flatpack  
14 Lead SBDIP  
o
ACTS86D/Sample  
ACTS86K/Sample  
ACTS86HMSR  
+25 C  
o
+25 C  
Sample  
14 Lead Ceramic Flatpack  
Die  
o
+25 C  
Die  
Truth Table  
Functional Diagram  
INPUTS  
OUTPUT  
An  
L
Bn  
L
Yn  
L
(1, 4, 9, 12)  
An  
(3, 6, 8, 11)  
Yn  
Bn  
L
H
L
H
H
L
(2, 5, 10, 13)  
H
H
H
NOTE: L = Logic Level Low, H = Logic Level High  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
Spec Number 518847  
File Number 3996  
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999  
1
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