Datasheet > ACS8510REV2.1

ACS8510REV2.1

更新时间： 2024-02-25 22:24:21

品牌	Logo	应用领域
商升特 - SEMTECH		/
页数	文件大小	规格书
76页	789K
描述
Synchronous Equipment Timing Source for SONET or SDH Network Elements

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ACS8510REV2.1 技术参数

生命周期：	Obsolete	包装说明：	,
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.77	电信集成电路类型：	ATM/SONET/SDH SUPPORT CIRCUIT
Base Number Matches：	1

ACS8510REV2.1 数据手册

ACS8510 Rev2.1 SETS

FINAL

ADVANCED COMMUNICATIONS

Table 3. Other Pins (continued)

SYMBOL

TO1

TYPE

TTL

NAME/DESCRIPTION

Output reference 1: default 6.48 MHz. Also Dig1 (1.544

CMOS MHz/2.048 MHz and 2, 4, 8 x), 19.44 MHz, 25.92 MHz

TTL Output reference 2: default 38.88 MHz. Also Dig2 (1.544

CMOS MHz/2.048 MHz and 2, 4, 8 x), 25.92 MHz, 51.84 MHz

TO2

TO3

TO4

TO5

TO9

TTL

Output reference 3: 19.44 MHz - fixed.

CMOS

TTL

Output reference 4: 38.88 MHz - fixed.

CMOS

TTL

Output reference 5: 77.76 MHz - fixed.

CMOS

TTL

Output reference 9: 1.544/2.048 MHz. (T4 BITS)

CMOS

MASTERSLAVEB: Master slave select: sets the initial power up

state (or state after a PORB) of the Master/Slave selection register,

addr 34, bit 1. The register state can be changed after power up by

software.

MSTSLVB

SONSDHB

TTL^U

SONETSDHB: SONET or SDH frequency select: sets the initial

power up state (or state after a PORB) of the SONET/SDH

frequency selection registers, addr 34h, bit 2 and addr 38, bits 5

and 6. The register states can be changed after power up by

software.

100

TTL_D

The ACS8510 supports all three types of

reference clock source: recovered line clock

Functional Description

The ACS8510 is a highly integrated, single-chip

solution for the SETS function in a SONET/SDH

Network Element, for the generation of SEC

and frame synchronization pulses. In Free-run

mode, the ACS8510 generates a stable, low-

noise clock signal from an internal oscillator.

In Locked mode, the ACS8510 selects the most

appropriate input reference source and

generates a stable, low-noise clock signal locked

to the selected reference. In Holdover mode,

the ACS8510 generates a stable, low-noise

clock signal from the internal oscillator,

adjusted to match the last known good

frequency of the last selected reference source.

In all modes, the frequency accuracy, jitter and

drift performance of the clock meet the

requirements of ITU G.812, G.813, G.823, and

GR-1244-CORE.

(T_IN1), PDH network synchronization timing (T_IN2)

and node synchronization (T_IN3). The ACS8510

generates independent T_OUT0and T_OUT4clocks,

an 8 kHz Frame Synchronization clock and a

2 kHz Multi-Frame Synchronization clock.

The ACS8510 has a high tolerance to input

jitter and wander. The jitter/wander transfer is

programmable (0.1 Hz up to 20 Hz cut-off

points).

The ACS8510 supports protection. Two

ACS8510 devices can be configured to provide

protection against a single ACS8510 failure.

The protection maintains alignment of the two

ACS8510 devices (Master and Slave) and

ensures that both ACS8510 devices maintain

the same priority table, choose the same

Revision 2.00/September 2003 Semtech Corp.

www.semtech.com

1...6 7 8910 11 12...76

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与ACS8510REV2.1相关器件

型号	品牌	获取价格	描述	数据表
ACS8510REV2.1SETS	ETC	获取价格	Synchronous Equipment Timing Source for SONET or SDH Network Elements
ACS8510REV2.1T	SEMTECH	获取价格	Support Circuit,
ACS8510T	SEMTECH	获取价格	暂无描述
ACS8512	SEMTECH	获取价格	ATM/SONET/SDH IC, PQFP64
ACS8514	SEMTECH	获取价格	Synchronous Equipment Timing Source Partner IC for 2nd T4 DPLL, Accurate Monitoring & Inpu
ACS8514T	SEMTECH	获取价格	Synchronous Equipment Timing Source Partner IC for 2nd T4 DPLL, Accurate Monitoring & Inpu
ACS8515	SEMTECH	获取价格	Line Card Protection Switch for SONET or SDH Network Elements
ACS8515LC	SEMTECH	获取价格	Line Card Protection Switch for SONET or SDH Network Elements
ACS8515P	SEMTECH	获取价格	Line Card Protection Switch for SONET or SDH Network Elements
ACS8515REV2.1	SEMTECH	获取价格	Line Card Protection Switch for SONET or SDH Network Elements

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