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ACS8510REV2.1 PDF预览

ACS8510REV2.1

更新时间: 2024-02-23 00:01:56
品牌 Logo 应用领域
商升特 - SEMTECH /
页数 文件大小 规格书
76页 789K
描述
Synchronous Equipment Timing Source for SONET or SDH Network Elements

ACS8510REV2.1 技术参数

生命周期:Obsolete包装说明:,
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.77电信集成电路类型:ATM/SONET/SDH SUPPORT CIRCUIT
Base Number Matches:1

ACS8510REV2.1 数据手册

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ACS8510 Rev2.1 SETS  
FINAL  
ADVANCED COMMUNICATIONS  
Crystal Frequency Calibration  
reference input and generate the TOUT0 clock,  
the 8 kHz Frame Synchronization clock and the  
2 kHz Multi-Frame Synchronization clock with  
the same phase. The ACS8510 includes a  
microprocessor port, providing access to the  
configuration and status registers for device  
setup and monitoring.  
The absolute crystal frequency accuracy is less  
important than the stability since any frequency  
offset can be compensated by adjustment of  
register values in the IC. This allows for  
calibration and compensation of any crystal  
frequency variation away from its nominal value.  
+/- 50 ppm adjustment would be sufficient to  
cope with most crystals, in fact the range is an  
order of magnitude larger due to the use of  
two 8 bit register locations. The setting of the  
conf_nominal_frequency register allows for this  
adjustment. An increase in the register value  
increases the output frequencies by 0.02 ppm  
for each LSB step. The default value (in decimal)  
is 39321. The minimum being 0 and the  
maximum 65535, gives a -700 ppm to  
+500 ppm adjustment range of the output  
frequencies.  
Local Oscillator Clock  
The Master system clock on the ACS8510  
should be provided by an external clock oscillator  
of frequency 12.80 MHz. The clock specification  
is important for meeting the ITU/ETSI and  
Telcordia performance requirements for  
Holdover mode. ITU and ETSI specifications  
permit a combined drift characteristic, at  
constant temperature, of all non-temperature-  
related parameters, of up to 10 ppb per day.  
The same specifications allow a drift of 1 ppm  
over a temperature range of 0 to +70 °C.  
Telcordia specifications are somewhat tighter,  
requiring a non-temperature-related drift of less  
than 40 ppb per day and a drift of 280 ppb  
over the temperature range 0 to +50 °C.  
For example, if the crystal was oscillating at  
12.8 MHz + 5 ppm, then the calibration value  
in the register to give a -5 ppm adjustment in  
output frequencies to compensate for the  
crystal inaccuracy, would be :  
ITU and ETSI Specification  
39321 - (5 / 0.02) = 39071 (decimal)  
Tolerance:  
Drift*:  
+/- 4.6 ppm over 20 year life time.  
+/- 0.05 ppm/15 seconds @ constant temp.  
+/- 0.01 ppm/day @ constant temp.  
+/- 1 ppm over temp. range 0 to +70 °C  
Input Interfaces  
The ACS8510 supports up to fourteen input  
reference clock sources from input types TIN1,  
TIN2 and TIN3 using TTL, CMOS, PECL, LVDS and  
AMI buffer I/O technologies. These interface  
technologies support +3.3 V and +5 V  
operation.  
*Frequency drift over supply range of +2.7V to +3.3V.  
Telcordia GR-1244 CORE Specification  
Tolerance:  
Drift*:  
+/- 4.6 ppm over 20 year life time.  
+/- 0.05 ppm/15 seconds @ constant temp.  
+/- 0.04 ppm/day @ constant temp.  
Over-Voltage Protection  
The ACS8510 may require Over-Voltage  
Protection on input reference clock ports  
according to ITU Recommendation K.41.  
Semtech protection devices are recommended  
for this purpose (see separate Semtech data  
book).  
+/- 0.28 ppm over temp. range 0 to +50 °C  
*Frequency drift over supply range of +2.7V to +3.3V.  
Please contact Semtech for information on  
crystal oscillator suppliers.  
Revision 2.00/September 2003 Semtech Corp.  
10  
www.semtech.com  

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