Datasheet > ACS8510REV2.1

ACS8510REV2.1

更新时间： 2024-02-29 07:55:00

品牌	Logo	应用领域
商升特 - SEMTECH		/
页数	文件大小	规格书
76页	789K
描述
Synchronous Equipment Timing Source for SONET or SDH Network Elements

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技术参数
数据手册

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ACS8510REV2.1 技术参数

生命周期：	Obsolete	包装说明：	,
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.77	电信集成电路类型：	ATM/SONET/SDH SUPPORT CIRCUIT
Base Number Matches：	1

ACS8510REV2.1 数据手册

ACS8510 Rev2.1 SETS

FINAL

ADVANCED COMMUNICATIONS

Table 3. Other Pins

SYMBOL

TRST

TYPE

TTL_D

NAME/DESCRIPTION

JTAG Control Reset Input: TRST = 1 to enable JTAG Boundary

Scan mode. TRST = 0 for normal device operation (JTAG logic

transparent). If not used connect to GND or leave floating.

JTAG Test Mode Select: Boundary Scan enable. Sampled on

rising edge of TCK. If not used connect to VDD or leave floating.

TMS

TTL^U

TTL

CMOS

INTREQ

Interrupt Request: Active high software Interrupt output

JTAG Clock: Boundary Scan clock input. If not used connect to

GND or leave floating. This pin may require a capacitor placed

between the pin and the nearest GND, to reduce noise pickup. A

value of 10 pF should be adequate, but the value is dependent on

PCB layout.

TCK

TTL_D

Reference Clock: 12.8 MHz (refer to section headed Local

Oscillator Clock)

REFCLK

SRCSW

TDO

TTL

TTL_D

Source Switching: Force Fast Source Switching

TTL

CMOS

JTAG Output: Serial test data output. Updated on falling edge of

TCK. If not used leave floating.

JTAG Input: Serial test data Input. Sampled on rising edge of TCK.

If not used connect to VDD or leave floating.

TDI

TTL^U

AMI

Input reference 1: composite clock 64 kHz + 8 kHz

Input reference 2: composite clock 64 kHz + 8 kHz

Output reference 8: composite clock, 64 kHz + 8 kHz negative

pulse

TO8NEG

TO8POS

FrSync

AMI

Output reference 8: composite clock, 64 kHz + 8 kHz positive

pulse

TTL

CMOS

Output reference 10: 8 kHz Frame Sync clock output (square

wave)

TTL

CMOS

Output reference 11: 2 kHz Multi-Frame Sync clock output

(square wave)

MFrSync

Output reference 6: default 38.88 MHz. Also Dig1 (1.544

MHz/2.048 MHz and 2, 4, 8 x), 19.44 MHz, 155.52 MHz, 311.04

MHz. Default type LVDS.

TO6POS

TO6NEG

LVDS

PECL

TO7POS

TO7NEG

PECL

LVDS

Output reference 7: default 19.44 MHz. Also 51.84 MHz, 77.76

MHz, 155.52 MHz. Default type PECL.

I5POS

I5NEG

LVDS

PECL

Input reference 5: default 19.44 MHz, default type LVDS

Input reference 6: default 19.44 MHz, default type PECL

I6POS

I6NEG

PECL

LVDS

Revision 2.00/September 2003 Semtech Corp.

www.semtech.com

1...4 5 678 9 10...76

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